W83977AF Information Storage Devices, Inc, W83977AF Datasheet - Page 59

• Manufacturer Part Number: W83977AF
• Description: W83877TF Plus Kbc, Cir, RTC
• Manufacturer: Information Storage Devices, Inc

Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if
TABLE 3-3 FIFO TRIGGER LEVEL
Bit 4, 5: Reserved
Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to
Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to
Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1
3.2.6
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3
bits.
BIT 7
the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.
UFR bit 0 = 1.
a logical 0 by itself after being set to a logical 1.
a logical 0 by itself after being set to a logical 1.
before other bits of UFR are programmed.
0
0
1
1
Interrupt Status Register (ISR) (Read only)
BIT 6
7
0
1
0
1
6
5
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
4
3
2
1
01
04
08
14
0
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
W83977F/ W83977AF
Publication Release Date: January 1997
PRELIMINARY
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Revision 0.50