W83977AF Information Storage Devices, Inc, W83977AF Datasheet - Page 79

• Manufacturer Part Number: W83977AF
• Description: W83877TF Plus Kbc, Cir, RTC
• Manufacturer: Information Storage Devices, Inc

4.7 Set 5 - Flow control and IR control and Frame Status FIFO registers
4.7.1 Set5.Reg0, 1 - Flow Control Baud Rate Divisor Latch Register (FCDLL/ FCDHL)
If flow control is enforced when UART switches mode from MIR/FIR to SIR, then the pre-programmed
baud rate of FCBLL/FCBHL are loaded into advanced baud rate divisor latch (ADBLL/ADBHL).
4.7.2 Set5.Reg2 - Flow Control Mode Operation (FC_MD)
These registers control flow control mode operation as shown in the following table.
Bit 7~5
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
Reset Value
Address Offset Register Name
FC_MD
Reg.
0
1
2
3
4
5
6
7
FC_MD2 FC_MD1 FC_MD0
FC_MD2 - Flow Control Mode
When flow control is enforced, these bits will be loaded into AD_MD2~0 of advanced
HSR (Handshake Status Register). These three bits are defined as same as AD_MD2~0.
Reserved, write 0.
FC_DSW - Flow Control DMA Channel Swap
A write to 1 allow user to swap DMA channel for transmitter or receiver when flow control
is enforced.
EN_FD - Enable Flow DMA Control
A write to 1 enables UART to use DMA channel when flow control is enforced.
EN_BRFC - Enable Baud Rate Flow Control
A write to 1 enables FC_BLL/FC_BHL (Flow Control Baud Rate Divider Latch, in
Set5.Reg1~0) to be loaded into advanced baud rate divisor latch (ADBLL/ADBHL, in
Set2.Reg1~0).
EN_FC - Enable Flow Control
A write to 1 enables flow control function and bit 7~1 of this register.
Bit 7
0
FC_DSW
RFRLFH
RFRLFL
IRCFG1
FCBHL
FC_MD
0
1
FCBLL
FS_FO
SSR
Bit 6
0
Flow Control Baud Rate Divisor Latch Register (Low Byte)
Flow Control Baud Rate Divisor Latch Register (High Byte)
Flow Control Mode Operation
Sets Select Register
Infrared Configure Register
Frame Status FIFO Register
Receiver Frame Length FIFO Low Byte
Receiver Frame Length FIFO High Byte
Bit 5
0
Next Mode After Flow Control Occurred
- 67 -
Bit 4
0
-
Transmitter Channel
Receiver Channel
FC_DSW
Register Description
W83977F/ W83977AF
Bit 3
0
Publication Release Date: March 1998
EN_FD
Bit 2
0
PRELIMINARY
EN_BRFC EN_FC
Bit 1
0
Revision 0.58
Bit 0
0