W83977AF Information Storage Devices, Inc, W83977AF Datasheet - Page 74

• Manufacturer Part Number: W83977AF
• Description: W83877TF Plus Kbc, Cir, RTC
• Manufacturer: Information Storage Devices, Inc

Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
4.4.3 Reg3 - Sets Select Register (SSR)
Reading this register returns E0H. Writing a value selects Register Set.
4.4.4 Reg4 - Advanced IR Control Register 2 (ADCR2)
Bit 7:
Bit 6:
Bit 5, 4:
Advanced IR DIS_BACK
Refault Value
Reset Value
Mode
Reg.
SSR
DMATHL
0
1
ALOOP - All Mode Loopback
A write to 1 will enable loopback in all modes.
D_CHSW - DMA TX/RX Channel Swap
If only one DMA channel operates in MIR/FIR mode, then the DMA channel can be
swapped.
A write to 1 will enable output data when ALOOP=1.
DMATHL - DMA Threshold Level
Set DMA threshold level as shown in the following table.
DMA_F - DMA Fairness
ADV_SL - Advanced Mode Select
A write to 1 selects advanced mode.
DIS_BACK - Disable Backward Operation
A write to 1 disables backward legacy IR mode. When operate in legacy SIR/ASK-IR
mode, this bit should be set to 1 to avoid backward operation.
Reserved, write 0.
PR_DIV1~0 - Pre-Divisor 1~0.
These bits select pre-divisor for external input clock 24M Hz. The clock goes through the
pre-divisor then input to baud rate divisor of IR.
SSR7
Bit 7
Bit 7
PR_DIV1~0
1
0
00
01
10
11
DMA_F
0
1
SSR6
Bit 6
D_CHSW
Bit 6
1
0
-
0
1
16-Byte
13
23
PR_DIV1 PR_DIV0 RX_FSZ1 RX_FSZ0 TX_FSZ1 TXFSZ0
SSR5
Bit 5
TX FIFO Threshold
Bit 5
1
0
Pre-divisor
DMA request (DREQ) is forced inactive after 10.5us
- 62 -
1.625
13.0
6.5
1
SSR4
Bit 4
DMA Channel Selected
Bit 4
0
0
Receiver (Default)
Transmitter
No effect DMA request.
Function Description
W83977F/ W83977AF
32-Byte
SSR3
Bit 3
Bit 3
Publication Release Date: March 1998
0
13
7
0
Max. Baud Rate
115.2K bps
921.6K bps
230.4K bps
1.5M bps
SSR2
Bit 2
Bit 2
0
0
RX FIFO Threshold
PRELIMINARY
(16/32-Byte)
SRR1
Bit 1
Bit 1
0
0
Revision 0.58
10
4
SRR0
Bit 0
Bit 0
0
0