W83977AF Information Storage Devices, Inc, W83977AF Datasheet - Page 80

• Manufacturer Part Number: W83977AF
• Description: W83877TF Plus Kbc, Cir, RTC
• Manufacturer: Information Storage Devices, Inc

4.7.3 Set5.Reg3 - Sets Select Register (SSR)
Writing this register selects Register Set. Reading this register returns ECH.
4.7.4 Set5.Reg4 - Infrared Configure Register 1 (IRCFG1)
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3~2:
Bit 1:
Bit 0:
4.7.5Set5.Reg5 - Frame Status FIFO Register (FS_FO)
This register shows the bottom byte of frame status FIFO.
Bit 7:
Bit 6:
Bit 5:
Reset Value
Reset Value
IRCFG1
FS_FO
Default Value
Reg.
Reg.
Reg.
SSR
FSFDR - Frame Status FIFO Data Ready
Indicate that a data byte is valid in frame status FIFO bottom.
LST_FR - Lost Frame
Set to 1 when one or more frames have been lost.
Reserved.
Reserved, write 0.
FSF_TH - Frame Status FIFO Threshold
Set this bit to determine the frame status FIFO threshold level and to generate the
FSF_I. The threshold level values are defined as follows.
FEND_MD - Frame End Mode
A write to 1 enables hardware to split data stream into equal length frame automatically
as defined in Set4.Reg4 and Set4.Reg5, i.e., TFRLL/TFRLH.
AUX_RX - Auxiliary Receiver Pin
A write to 1 selects IRRX input pin. (Refer to Set7.Reg7.Bit5)
Reserved, write 0.
IRHSSL - Infrared Handshake Status Select
When set to 0, the HSR (Handshake Status Register) operates as same as defined in IR
mode. A write to 1 will disable HSR, and reading HSR returns 30H.
IR_FULL - Infrared Full Duplex Operation
When set to 0, IR module operates in half duplex. A write to 1 makes IR module operate
in full duplex.
FSFDR
Bit 7
Bit 7
0
0
-
SSR7
Bit 7
1
FSF_TH
0
1
FSF_TH
LST_FR
Bit 6
Bit 6
0
0
SSR6
Bit 6
1
FEND_M AUX_RX
Bit 5
Bit 5
SSR5
0
0
-
Bit 5
1
- 68 -
MX_LEX PHY_ERR CRC_ERR RX_OV
Status FIFO Threshold Level
Bit 4
Bit 4
SSR4
Bit 4
0
0
0
W83977F/ W83977AF
Bit 3
Bit 3
SSR3
Bit 3
0
0
-
Publication Release Date: March 1998
2
4
1
Bit 2
Bit 2
SSR2
Bit 2
0
0
-
1
PRELIMINARY
IRHSSL
SRR1
Bit 1
Bit 1
Bit 1
0
0
0
Revision 0.58
IR_FULL
FSF_OV
SRR0
Bit 0
Bit 0
Bit 0
0
0
0