W83977AF Information Storage Devices, Inc, W83977AF Datasheet - Page 78

• Manufacturer Part Number: W83977AF
• Description: W83877TF Plus Kbc, Cir, RTC
• Manufacturer: Information Storage Devices, Inc

Bit 1:
Bit 0:
4.6.3 Set4.Reg3 - Set Select Register (SSR)
Reading this register returns E8H. Writing this register selects Register Set.
4.6.4 Set4.Reg4, 5 - Transmitter Frame Length (TFRLL/TFRLH)
These are combined to be a 13-bit register. Writing these registers programs the transmitter frame
length of a package.
Set5.Reg4.bit5). When APM=1, the physical layer will split data stream to a programmed frame
length if the transmitted data is larger than the programmed frame length. When these registers are
read, they will return the number of bytes which is not transmitted from a frame length programmed.
4.6.5 Set4.Reg6, 7 - Receiver Frame Length (RFRLL/RFRLH)
These are combined to be a 13-bit registers and up counter. The length of receiver frame will be
limited to the programmed frame length. If the received frame length is larger than the programmed
receiver frame length, the bit of MX_LEX (Maximum Length Exceed) will be set to 1. Simultaneously,
the receiver will not receive any more data to RX FIFO until the next start flag of the next frame,
which is defined in the physical layer IrDA 1.1. Reading these registers returns the number of
received data bytes of a frame from the receiver.
Reset Value
Reset Value
Reset Value
Reset Value
RFRLL
Default Value
TFRLL
RFRLH
TFRLH
Reg.
Reg.
Reg.
SSR
TMR_TST - Timer Test
When set to 1, reading the TMRL/TMRH returns the programmed values of TMRL/TMRH
instead of the value of down counter. This bit is for testing timer register.
EN_TMR - Enable Timer
A write to 1 will enable the timer.
Bit 7
Bit 7
bit 7
bit 7
0
0
-
-
-
-
SSR7
Bit 7
1
These registers are only valid when APM=1 (automatic package mode,
Bit 6
Bit 6
bit 6
bit 6
0
0
-
-
-
-
SSR6
Bit 6
1
Bit 5
Bit 5
bit 5
bit 5
SSR5
0
0
-
-
-
-
Bit 5
1
- 66 -
bit 12
bit 12
Bit 4
Bit 4
bit 4
bit 4
SSR4
Bit 4
0
0
0
0
1
W83977F/ W83977AF
bit 11
bit 11
Bit 3
Bit 3
bit 3
bit3
SSR3
Bit 3
0
0
0
0
Publication Release Date: March 1998
1
bit 10
bit 10
Bit 2
Bit 2
bit 2
bit 2
SSR2
Bit 2
0
0
0
0
0
PRELIMINARY
SRR1
Bit 1
Bit 1
bit 1
bit 9
bit 1
bit 9
Bit 1
0
0
0
0
0
Revision 0.58
SRR0
Bit 0
Bit 0
Bit 0
bit 0
bit 8
bit 0
bit 8
0
0
0
0
0