W83977AF Information Storage Devices, Inc, W83977AF Datasheet - Page 73

• Manufacturer Part Number: W83977AF
• Description: W83877TF Plus Kbc, Cir, RTC
• Manufacturer: Information Storage Devices, Inc

4.3.1 Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL)
These two registers of BLL and BHL are baud rate divisor latch in the legacy SIR/ASK-IR mode.
Accessing these registers in Advanced IR mode will cause backward operation, that is, UART will fall
back to legacy SIR mode and clear some register values as shown in the following table.
Note that DIS_BACK=1 (Disable Backward operation) in legacy SIR/ASK-IR mode will not affect any
register which is meaningful in legacy SIR/ASK-IR.
4.3.2 Set1.Reg 2~7
These registers are defined as the same as Set 0 registers.
4.4 Set2 - Interrupt Status or IR FIFO Control Register (ISR/UFR)
These registers are only used in advanced modes.
4.4.1
These two registers are the same as legacy IR baud rate divisor latch in SET 1.Reg0~1. In advanced
SIR/ASK-IR mode, user should program these registers to set baud rate. This is to prevent backward
operation from occurring.
4.4.2
Bit 7:
Bit 6:
Bit 5:
Advanced IR BR_OUT
Address Offset Register Name
Reset Value
Mode
Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL)
Reg2 - Advanced IR Control Register 1 (ADCR1)
0
1
2
3
4
5
6
7
BR_OUT - Baud Rate Clock Output
When written to 1, the programmed baud rate clock will be output to DTR pin. This bit is
only used to test baud rate divisor.
Reserved, write 0.
EN_LOUT - Enable Loopback Output
A write to 1 will enable transmitter to output data to IRTX pin when loopback operation.
Internal data can be verified through an output pin by setting this bit.
Set & Register
Set 0.Reg 4
Set 2.Reg 2
Set 4.Reg 3
Bit 7
0
Reserved
RXFDTH
TXFDTH
ADCR1
ADCR2
ABHL
ABLL
SSR
Bit 6
0
-
EN_LOUT
Advanced Baud Rate Divisor Latch (Low Byte)
Advanced Baud Rate Divisor Latch (High Byte)
Advanced IR Control Register 1
Sets Select Register
Advanced IR Control Register 2
Transmitter FIFO Depth
Receiver FIFO Depth
Bit 5
0
Advanced Mode
- 61 -
DIS_BACK= ¡Ñ
Bit 0, 5, 7
ALOOP D_CHSW DMATHL
Bit 7~5
Bit 2, 3
Bit 4
0
Register Description
W83977F/ W83977AF
Bit 3
Publication Release Date: March 1998
0
-
Bit 2
0
Legacy Mode
DIS_BACK=0
Bit 5, 7
PRELIMINARY
-
-
DMA_F
Bit 1
0
Revision 0.58
ADV_SL
Bit 0
0