lpc1778 NXP Semiconductors, lpc1778 Datasheet - Page 58

• Manufacturer Part Number: lpc1778
• Description: 32-bit Arm Cortex-m3 Microcontroller; Up To 512 Kb Flash And 96 Kb Sram; Usb Device/host/otg; Ethernet; Lcd; Emc
• Manufacturer: NXP Semiconductors

NXP Semiconductors
LPC178x_7x
Objective data sheet
7.23.1 Features
7.24.1 Features
7.23 I
7.24 CAN controller and acceptance filters
The LPC178x/7x contain one I
communication interface for digital audio applications.
The I
and one word select signal. The basic I
master, and one slave. The I
and receive channel, each of which can operate as either a master or a slave.
The LPC178x/7x contain two CAN controllers.
The Controller Area Network (CAN) is a serial communications protocol which efficiently
supports distributed real-time control with a very high level of security. Its domain of
application ranges from high-speed networks to low cost multiplex wiring.
The CAN block is intended to support multiple CAN buses simultaneously, allowing the
device to be used as a gateway, switch, or router between two of CAN buses in industrial
or automotive applications.
Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN
Library block, but the 8-bit registers of those devices have been combined in 32-bit words
to allow simultaneous access in the ARM environment. The main operational difference is
that the recognition of received Identifiers, known in CAN terminology as Acceptance
Filtering, has been removed from the CAN controllers and centralized in a global
Acceptance Filter.
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S-bus serial I/O controllers
The I
Both I
mode.
The interface has separate input/output channels each of which can operate in master
or slave mode.
Capable of handling 8-bit, 16-bit, and 32-bit word sizes.
Mono and stereo audio data supported.
The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1,
48) kHz.
Configurable word select period in master mode (separately for I
Two 8 word FIFO data buffers are provided, one for transmit and one for receive.
Generates interrupt requests when buffer levels cross a programmable boundary.
Two DMA requests, controlled by programmable buffer levels. These are connected
to the GPDMA block.
Controls include reset, stop and mute options separately for I
Two CAN controllers and buses.
2
S-bus specification defines a 3-wire serial bus using one data line, one clock line,
2
2
C-bus can be used for test and diagnostic purposes.
C-bus controllers support multiple address recognition and a bus monitor
All information provided in this document is subject to legal disclaimers.
Rev. 00.04 — 8 July 2010
2
S interface on the LPC178x/7x provides a separate transmit
2
S-bus interface. The I
2
S connection has one master, which is always the
32-bit ARM Cortex-M3 microcontroller
2
S-bus provides a standard
LPC178x/7x
2
S input and I
2
S input and output).
© NXP B.V. 2010. All rights reserved.
2
S output.
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