p89v51rb2 NXP Semiconductors, p89v51rb2 Datasheet - Page 44

• Manufacturer Part Number: p89v51rb2
• Description: 8-bit 80c51 5 V Low Power 16/32/64 Kb Flash Microcontroller With 1 Kb Ram
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89V51RB2_RC2_RD2_4
Product data sheet
Fig 18. SPI transfer format with CPHA = 0
SCK (CPOL = 0)
SCK (CPOL = 1)
(for reference)
(from master)
SS (to slave)
SCK cycle #
(from slave)
Table 29.
Table 30.
Table 31.
Bit addressable; Reset source(s): any reset; Reset value: 0000 0000B
Table 32.
Bit
2
1
0
SPR1
0
0
1
1
Bit
7
6
5 to 0
Bit
Symbol
MOSI
MISO
SPCR - SPI control register (address D5H) bit description
SPCR - SPI control register (address D5H) clock rate selection
SPSR - SPI status register (address AAH) bit allocation
SPSR - SPI status register (address AAH) bit description
Symbol
CPHA
SPR1
SPR0
Symbol
SPIF
WCOL
-
SPIF
7
MSB
MSB
1
WCOL
2
SPR0
0
1
0
1
6
6
Rev. 04 — 1 May 2007
6
Description
Clock Phase control bit. 1 = shift triggered on the trailing edge of the
clock; 0 = shift triggered on the leading edge of the clock.
SPI Clock Rate Select bit 1. Along with SPR0 controls the SCK rate of
the device when a master. SPR1 and SPR0 have no effect on the
slave. See
SPI Clock Rate Select bit 0. Along with SPR1 controls the SCK rate of
the device when a master. SPR1 and SPR0 have no effect on the
slave. See
Description
SPI interrupt flag. Upon completion of data transfer, this bit is set to ‘1’.
If SPIE = 1 and ES = 1, an interrupt is then generated. This bit is
cleared by software.
Write Collision Flag. Set if the SPI data register is written to during
data transfer. This bit is cleared by software.
Reserved for future use. Should be set to ‘0’ by user programs.
3
5
5
4
5
-
4
4
Table 30
Table 30
5
3
3
P89V51RB2/RC2/RD2
below.
below.
4
-
SCK = f
4
16
64
128
6
2
2
8-bit microcontrollers with 80C51 core
7
1
1
osc
3
-
divided by
LSB
LSB
8
2
-
002aaa529
…continued
© NXP B.V. 2007. All rights reserved.
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