mc9s12uf32 Freescale Semiconductor, Inc, mc9s12uf32 Datasheet - Page 35
mc9s12uf32
Manufacturer Part Number
mc9s12uf32
Description
System Chip Guide V01.05
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12UF32.pdf
(128 pages)
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NOTES:
1. These registers are mapped to the registers on an external ATA/ATAPI device, for detail explanation of the #, #r1,
#r2, #w, #1,#2 field, please refer to the ATAHC block guide and ATA/ATAPI standards.
DCR/DSR (hi)
DFR/DER (hi)
DFR/DER (lo)
DCTR/DASR
DCTR/DASR
HUDMA9 (lo)
HDMAM (lo)
DSCR (hi)
DSCR (lo)
DSNR (hi)
DSNR (lo)
DCHR (hi)
DCHR (lo)
DDHR (hi)
DDHR (lo)
DCLR (hi)
DCLR (lo)
Reserved
DDR (hi)
DDR (lo)
Name
(hi)
(lo)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
ATA Host Controller (ATA5HC)
Bit 7
BSY
BSY
obs
PIE
0
0
0
0
0
0
0
0
0
DRDY
DRDY
Bit 6
HUT
#1
0
0
0
0
0
0
0
0
0
System on a Chip Guide — 9S12UF32DGV1/D V01.05
Bit 5
obs
#r1
AF
0
0
0
0
0
0
0
0
0
#r
#
Bit 4
DEV
0
0
0
0
0
0
0
0
0
0
BYTE_O
BYTE_E
#w
#w
#
#
#
#
DRQ
DRQ
Bit 3
IE
0
0
0
0
0
0
0
0
0
UDMA
SRST
ABRT
Bit 2
0
0
0
0
0
0
0
0
0
obs
obs
#2
nIEN
Bit 1
RD
0
0
0
0
0
0
0
0
0
#r2
ZERO
ERR
ERR
Bit 0
WR
0
0
0
0
0
0
0
0
0
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