r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 180
r5f21368sdfp
Manufacturer Part Number
r5f21368sdfp
Description
Renesas Mcu R8c Family / R8c/3xt-a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5F21368SDFP.pdf
(760 pages)
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Part Number:
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Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 11.9
Figure 11.10
11.5.2
Sampling timing
INTiIC register
Note:
The INTi input includes a digital filter. The sampling clock can be selected by bits INTiF0 and INTiF1 in
registers INTF and INTF1. The INTi level is sampled every sampling clock cycle, and the corresponding IR bit
in the INTiIC register is set to 1 (interrupt requested) when the sampled input level matches three successive
times.
Figure 11.9 shows the INTi Input Filter Configuration and Figure 11.10 shows an Example of INTi Input Filter
Operation.
INTi input
1. In this example, bits INTiF1 and INTiF0 in the INTF0 register are set to 01b, 10b, or 11b (filter used).
INTi
IR bit in
f32
f1
f8
INTiF1 and INTiF0
INTi Input Filter (i = 0 to 4)
INTiF0, INTiF1: Bits in registers INTF0 and INTF1
INTiEN, INTiPL: Bits in registers INTEN0 and INTEN1
INTiPOL: Bit in INTPOL register
= 01b
= 10b
= 11b
Preliminary document
Specifications in this document are tentative and subject to change.
INTi Input Filter Configuration (i = 0 to 4)
Example of INTi Input Filter Operation (i = 0 to 4)
Sampling clock
If the level does not match three
Digital filter
times, it is assumed to be noise
and the IR bit does not change
(matches
3 times)
Other than
INTiF1 and INTiF0
= 00b
= 00b
Both edges
detection
circuit
Since the level matched
three times, it is recognized
as a signal change and the
IR bit is set to 1
INTiPOL = 1
INTiPOL = 0
INTiPL = 0
INTiPL = 1
INTiEN
INTi interrupt request
Output for ELC
Peripheral trigger
Set to 0 by a program
Page 149 of 725
11. Interrupts
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