r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 535
r5f21368sdfp
Manufacturer Part Number
r5f21368sdfp
Description
Renesas Mcu R8c Family / R8c/3xt-a Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R5F21368SDFP.pdf
(760 pages)
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Part Number:
r5f21368sdfp#V0
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Renesas Electronics America
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Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 21.28
21.4.3
21.4.3.1
When the MS bit in the SIMR2 register is set to 1, clock synchronous serial format is used for communication.
Figure 21.28 shows the Transfer Format for Clock Synchronous Serial Mode.
When the MST bit in the SICR1 register is 1, the transfer clock is output from the SCL pin. When the MST bit
is set to 0, the external clock is input.
The transfer data is output between successive falling edges of the SCL clock, and data is determined at the
rising edge of the SCL clock. MSB first or LSB first can be selected as the order of the data transfer by setting
the MLS bit in the SIMR1 register. The SDA output level can be changed by the SDAO bit in the SICR2
register during transfer standby.
Clock Synchronous Serial Mode
SCL
SDA
Preliminary document
Specifications in this document are tentative and subject to change.
Clock Synchronous Serial Format
Transfer Format for Clock Synchronous Serial Mode
b0
b1
b2
b3
b4
b5
21. Clock Synchronous Serial Interface
b6
b7
Page 504 of 725
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