km416s1120d ETC-unknow, km416s1120d Datasheet - Page 10

• Manufacturer Part Number: km416s1120d
• Description: 512k X 16bit X 2 Banks Synchronous Dram Lvttl
• Manufacturer: ETC-unknow

Register Programmed with MRS
KM416S1120D
MODE REGISTER FIELD TABLE TO PROGRAM MODES
POWER UP SEQUENCE
1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal operation.
Note : 1. If A
SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
Address
Function
A
A
0
0
1
1
0
1
8
9
2. RFU (Reserved for future use) should stay "0" during MRS cycle.
Write Burst Length
A
0
1
0
1
7
RFU
9
Test Mode
BA
is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
Mode Register Set
Single Bit
Length
Burst
Reserved
Reserved
Reserved
A
Type
RFU
10
/AP
W.B.L
A
9
A
0
0
0
0
1
1
1
1
6
A
A
CAS Latency
0
0
1
1
0
0
1
1
8
5
TM
A
0
1
0
1
0
1
0
1
4
A
7
Reserved
Reserved
Reserved
Reserved
Reserved
Latency
- 10
2
3
-
A
6
CAS Latency
A
0
1
3
Burst Type
A
5
Sequential
Interleave
Full Page Length : x4 (1024), x8 (512), x16 (256)
Type
A
4
A
0
0
0
0
1
1
1
1
2
A
BT
3
A
0
0
1
1
0
0
1
1
1
CMOS SDRAM
Rev. 1.4 (Jun. 1999)
A
A
Burst Length
0
1
0
1
0
1
0
1
0
2
Reserved
Reserved
Reserved
Full Page
Burst Length
BT = 0
1
2
4
8
A
1
Reserved
Reserved
Reserved
Reserved
BT = 1
A
1
2
4
8
0