km416s1120d ETC-unknow, km416s1120d Datasheet - Page 19

• Manufacturer Part Number: km416s1120d
• Description: 512k X 16bit X 2 Banks Synchronous Dram Lvttl
• Manufacturer: ETC-unknow

KM416S1120D
6. Precharge
7. Auto Precharge
*Note : 1. t
1) Normal Write (BL=4)
2) Normal Read (BL=4)
1) Normal Write (BL=4)
2) Normal Read (BL=4)
2. Number of valid output data after row precharge : 0, 1, 2 for CAS Latency =1, 2, 3 respectively.
3. The row active command of the precharge bank can be issued after t
DQ(CL2)
DQ(CL3)
DQ(CL2)
DQ(CL3)
The new read/write command of the other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/other bank is illegal.
RDL
CMD
CMD
CMD
CMD
CLK
CLK
CLK
CLK
DQ
DQ
: Last data in to row precharge delay
RD
WR
RD
WR
D
D
0
0
D
D
1
1
D
D
Q
Q
2
2
0
0
D
D
Q
Q
Q
Q
3
3
1
0
1
0
tRDL
Note 2
Auto Precharge Starts
Auto Precharge Starts
PRE
PRE
Q
Q
Q
Q
2
2
1
1
Q
Q
Q
Q
Note 3
Note 3
3
2
3
2
1
Note 2
- 19
Q
Q
3
3
2
RP
from this point.
CMOS SDRAM
Rev. 1.4 (Jun. 1999)