km416s1120d ETC-unknow, km416s1120d Datasheet - Page 21

• Manufacturer Part Number: km416s1120d
• Description: 512k X 16bit X 2 Banks Synchronous Dram Lvttl
• Manufacturer: ETC-unknow

KM416S1120D
10. Clock Suspend Exit & Power Down Exit
11. Auto Refresh & Self Refresh
*Note : 1. Active power down : one or both banks active state.
1) Clock Suspend (=Active Power Down) Exit
1) Auto Refresh & Self Refresh
2) Self Refresh
2. Precharge power down : both banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
4. Before executing auto/self refresh command, both banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refresh operation are perfomed internally.
Internal
For the time interval of t
No precharge commands are required after auto refresh command.
During t
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh mode, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state.
auto refresh cycle (2048 cycles) is recommended.
CMD
CMD
CMD
CKE
CLK
CLK
CLK
CKE
CLK
CKE
RFC
from auto refresh command, any other command can not be accepted.
Note 6
Note 1
PRE
PRE
RFC
Note 4
Note 4
from self refresh exit command, any other command can not be accepted. Before/After self refresh mode, burst
tRP
tRP
Note 3
tSS
SR
AR
RD
tRFC
¡ó
¡ó
¡ó
¡ó
¡ó
¡ó
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2) Power Down (=Precharge Power Down)
Internal
¡ó
CMD
CMD
CKE
CLK
CLK
tRFC
Note 5
Note 2
CMD
NOP
CMOS SDRAM
tSS
Rev. 1.4 (Jun. 1999)
ACT