lf3324 LOGIC Devices Incorporated, lf3324 Datasheet - Page 25

• Manufacturer Part Number: lf3324
• Description: 24mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

Random Access Write Pointer ‘Jump’ Timing
Output Enable and Disable
Jumping/Setting Pointers based on Configuration Register Address after Remapping Process
DEVICES INCORPORATED
LOGIC Devices Incorporated
Q[11:0]
OE
ADDR
D[11:0]
WCLK
WSET
1
2
3
4
WEN is LOW for 3 rising edges of WCLK prior to LOAD transition. It stays LOW for the minimum required 5 rising edges after the LOAD transition.
The configuration registers are programmed while LOAD is LOW. The LOAD transition triggers the address remap process.
WSET can be brought LOW (edge "3") 3 rising edges of WCLK after the LOAD transition, jumping the write pointer to the address programmed into the WADR register.
RSET can be brought LOW (edge "7") 7 rising edges of RCLK after the LOAD transition, jumping the read pointer to the address programmed into the RADDR register.
WSET
RSET
WCLK
LOAD
23–0
WEN
WEN= LOW WADDRSEL= HIGH
NOTE: SET programmed to be falling edge sensitive
NOTE: Rising edge of WCLK labeled "1" writes data on D to 24bit Address "A"
SET and RSET programmed to be level sensitive
2
3
4
1
(n)
(n+1)
t
RWH
OPMODE[2:0]=001
t
RWS
t
DS
A
(A)
23-0
1
1
t
DH
t
DIS
2
(A+1)
25
t
RWS
3
t
RWH
(A+2)
HIGH IMPEDANCE
4
5
t
24Mbit Frame Buffer / FIFO
RWH
(A+3)
t
ENA
Preliminary Datasheet
6
Video Imaging Product
t
RWS
(A+4)
7
June 8, 2007 LDS.3324 G
t
RWH
LF3324