lf3324 LOGIC Devices Incorporated, lf3324 Datasheet - Page 5

• Manufacturer Part Number: lf3324
• Description: 24mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LOGIC Devices Incorporated
Operating Modes
through setting (jumping) the write pointer to the 24bit address via the ADDR[23:0] port or to the WADDR
configuration register. Read pointer manipulation can be done through setting (jumping) the write pointer
to the 24bit address via the ADDR[23:0] port or to the RADDR configuration register. Periodic write and
read pointer jumping can be accomplished by supplying an address through either the ADDR[23:0] external
address or the WADDR/RADDR instruction registers. Continuous random access can only be accomplished
through the use of the ADDR[23:0] ports. When the write/read pointers are not being set to an address,
they increment sequentially in burst mode.
In Random Access Mode, when WADRSEL = 1 and RADRSEL = 0 the write pointer is set to the address
supplied by the ADDR[23:0] ports when WSET is brought LOW. In other words, on each active write clock
cycle (rising edge of WCLK for which WEN was LOW two rising edges of WCLK previously), the user
directs the write pointer to any desired memory location, using what are otherwise the second channel
data input and output ports. In this application, ADDR[23:12] denotes the vertical (row) component,
and ADDR[11:0], the horizontal (column) component, of a Cartesian set. Setting the configuration
register ROW_LENGTH to the frame’s line (row) length internally defines the Cartesian coordinates. Also,
ADDR[23:0] can also represent a single 24-bit linear address. The user governs the mapping of (ADDR)
to the internal memory space by setting the parameter ROW_LENGTH such that the internal ADDRESS
= ADDR[23-12] * ROW_LENGTH + ADDR[11-0]. A ROW_LENGTH setting of 0 is interpreted as 4096,
such that ADDRESS = a 24-bit concatenation of {ADDR} for this particular value. For a standard D1 video
application with 1716 samples per line, the user would set ROW_LENGTH to 1716 decimal = 6B4 hex.
Offset circuitry within the LF3324 permits the user to cascade several chips in parallel and to use them
collectively as a single large memory with a seamless address space. Data are read out sequentially by
rising edges of RCLK, under the control of REN (read enable), RSET (read pointer force to constant), and
RCLR (read pointer clear to 0). Holding WSET LOW keeps the device continuously in random access
write mode. Releasing WSET to its HIGH state causes the chip to continue to write sequentially from
the last-loaded address.
In Random Access Mode, when RADRSEL = 1, WADRSEL = 0, MARK_SEL = 1, the read pointer is set
to the address supplied by the ADDR[23:0] ports when RSET is brought LOW. As mentioned above,
ADDR[23:12] represents the upper bits or the vertical (row) address, whereas ADDR[11:0] represents the
lower bits or the horizontal (column) address. Releasing RSET HIGH causes the read address pointer to
increment from its last assigned location to the next sequential address.
It is important to note that WSET and RSET can be programmed to be level or negative-edge triggered.
An edge sensitive “SET” command is useful for using SYNC signals to reset FIFO pointers. Level sensitive
“SET” commands allow full-time Random Access capability.
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24Mbit Frame Buffer / FIFO
Preliminary Datasheet
Video Imaging Product
June 8, 2007 LDS.3324 G
LF3324