lf3324 LOGIC Devices Incorporated, lf3324 Datasheet - Page 15

• Manufacturer Part Number: lf3324
• Description: 24mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LOGIC Devices Incorporated
Configuration Register Map
Configuration Register 8 (default = 10_00_0_111)
7:6 = WIDTH[1:0]
5:4 = Reserved
3
2:0 = OPMODE
Configuration Register 9 (default = 00_000_000)
7:6 = TRS_SYNC[1:0]
5
4
3
2:0 = FLAG_SET
Configuration Register A (default = 00000000)
7
6
5
4
3
2
1
0
Configuration Register B (default = 00_00_00_00)
7:4 = -------
3:0 = FLAG_CTL
Configuration Register C (default = 0000_0000)
7:4 = BASE_ADDR
3:0 = CASCADE
= MARK_ACTIVE_RSET
= -------
= A_FLD
= MARK_SEL
= -------
= WSET_catch
= RSET_b_sel
= RCLR_b_sel
= -------
= -------
= WSET_b_sel
= WCLR_b_sel
(00: ignore embedded TRS)
Reserved - set to 0
(0: frame sync - use falling F-bit from TRS)
(0: use marked address - not user defined address)
(000: trigger empty, full on 1/80, 79/80)
(10: 10 bits)
(Make equal to 00)
(Make equal to 0)
(111)
Reserved - set to 0
(0: setting pointer does not MARK its new value)
(0: RSET is falling edge triggered)
(0: RCLR is falling edge triggered)
Reserved - set to 0
Reserved - set to 0
(0: WSET is falling edge triggered)
(0: WCLR is falling edge triggered)
15
(0000: lowest-address chip in cascade sequence)
(0000: single chip - no cascade of multiple chips)
RESERVED
(00: PE, PF are part-empty, -full)
24Mbit Frame Buffer / FIFO
Preliminary Datasheet
Video Imaging Product
June 8, 2007 LDS.3324 G
LF3324