lf3324 LOGIC Devices Incorporated, lf3324 Datasheet - Page 27

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lf3324

Manufacturer Part Number
lf3324
Description
24mbit Frame Buffer / Fifo
Manufacturer
LOGIC Devices Incorporated
Datasheet
DEVICES INCORPORATED
LOGIC Devices Incorporated
10. Each parameter is shown as a minimum or maximum value. Input requirements are specified
from the point of view of the external system driving the chip. Setup time, for example, is specified
as a minimum since the external system must supply at least that much time to meet the worst-
case requirements of all parts. Responses from the internal circuitry are specified from the point of
view of the device. Output delay, for example, is specified as a maximum since worst-case opera-
tion of any device always provides data within that time.
11. For the t ena test, the transition is measured to the 1.5 V crossing point with datasheet loads.
For the t dis test, the transition is measured to the ±200mV level from the measured steady-state
output voltage with ±10mA loads. The balancing voltage, V th , is set at 3.0 V for Z-to-0 and 0-to-Z
tests, and set at 0 V for Z-to-1 and 1-to-Z tests.
12. These parameters are only tested at the high temperature extreme, which is the worst case
for leakage current.
Notes
F
IGURE
DUT
A. O
C
UTPUT
L
S1
L
OADING
I
OH
C
IRCUIT
V
TH
27
I
OL
F
Z
Z
IGURE
OE
0
1
V
V
OH
OL
*
*
B. T
Measured V
Measured V
1.5 V
t
24Mbit Frame Buffer / FIFO
ENA
HRESHOLD
1.5 V
1.5 V
OL
OH
Preliminary Datasheet
with I
with I
Video Imaging Product
OH
OH
V
V
L
OL
OH
= –10mA and I
= –10mA and I
1.5 V
EVELS
*
*
0.2 V
0.2 V
t
DIS
June 8, 2007 LDS.3324 G
OL
OL
= 10mA
= 10mA
LF3324
3.0V Vth
0
1
0V Vth
Z
Z

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