tc59lm814 TOSHIBA Semiconductor CORPORATION, tc59lm814 Datasheet - Page 10

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tc59lm814

Manufacturer Part Number
tc59lm814
Description
256mbits Network Fcram1
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet

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Command
Address
POWER UP SEQUENCE
NOTES:
V
V
CLK
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
DQS
CLK
V
DDQ
DQ
REF
PD
DD
(1)
(2)
As for PD , being maintained by the low state (≤ 0.2 V) is desirable before a power-supply injection.
Apply V
Apply V
Start clock (CLK, CLK ) and maintain stable condition for 200 µs (min).
After stable power and clock, apply DESL and take PD =H.
Issue EMRS to enable DLL and to define driver strength. (Note: 1)
Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1)
Issue two or more Auto-Refresh commands (Note: 1).
Ready for normal operation after 200 clocks from Extended Mode Register programming.
Sequence 6, 7 and 8 can be issued in random order.
L = Logic Low, H = Logic High
DD
DDQ
200 us(min)
before or at the same time as V
before or at the same time as V
t
PDEX
Hi-Z
DESL
l
PDA
2.5V(TYP)
1.25V(TYP)
2.5V(TYP)
RDA
EMRS
MRS
op-code
EMRS
DESL
l
RSC
DDQ
REF
RDA MRS
.
.
MRS
op-code
MRS
l
RSC
DESL WRA REF
200clock cycle(min)
TC59LM814/06CTG-50,-60
DESL
l
REFC
Auto Refresh cycle
WRA REF
2005-06-21 10/39
DESL
l
REFC
Normal Operation
Rev 1.2

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