tc59lm814 TOSHIBA Semiconductor CORPORATION, tc59lm814 Datasheet - Page 33

• Manufacturer Part Number: tc59lm814
• Description: 256mbits Network Fcram1
• Manufacturer: TOSHIBA Semiconductor CORPORATION

COMMAND FUNCTIONS and OPERATIONS
Down mode, each operation mode decided by the combination of the first command and the second command from
stand-by states of the bank to be accessed.
TC59LM814/06CTG are introduced the two consecutive command input method. Therefore, except for Power
Read Operation (1st command + 2nd command = RDA + LAL)
Write Operation (1st command + 2nd command = WRA + LAL)
designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the
next clock of the WRA command, the input data is latched sequentially synchronizing with the both edges of
DQS input signal (Burst Write Operation). The data and DQS inputs have to be asserted in keeping with clock
input after CAS latency-1 from the issuing of the LAL command. The DQS have to be provided for a burst
length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write operated
bank goes back automatically to the idle state after l
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
with the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all
banks are in the idle state. In a point to notice, the write mode started with the WRA command is canceled by
the REF command having gone into the next clock of the WRA command instead of the LAL command. The
minimum period between the Auto-Refresh command and the next command is specified by l
about a synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distributed
refresh, Auto-Refresh command has to be issued within once for every 7.8 µs by the maximum. In case of burst
refresh or random distributed refresh, the average interval of eight consecutive Auto-Refresh command has to
be more than 400 ns always. In other words, the number of Auto-Refresh cycles which can be performed within
3.2 µs (8 × 400 ns) is to 8 times in the maximum.
Self-Refresh Operation (1st command + 2nd command = WRA + REF with
internal timer. When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM814/06CTG
become Self-Refresh mode by issuing the Self-Refresh command. PD has to be brought to “Low” within t
from the REF command following to the WRA command for a Self-Refresh mode entry. In order to satisfy the
refresh period, the Self-Refresh entry command should be asserted within 7.8 µs after the latest Auto-Refresh
command. Once the device enters Self-Refresh mode, the DESL command must be continued for l
In addition, it is necessary that clock input is kept in l
the power dissipation lowers. Regarding a Self-Refresh mode exit, PD has to be changed over from “Low” to
“High” along with the DESL command, and the DESL command has to be continuously issued in the number of
clocks specified by l
Auto-Refresh command is issued to avoid the violation of the refresh period just after l
exit.
Power Down Mode (
Down Mode by asserting PD is “Low”. When the device enters the Power Down Mode, all input and output
buffers except for PD are disabled after specified time. Therefore, the power dissipation lowers. To exit the
Power Down Mode, PD has to be brought to “High” and the DESL command has to be issued at next CLK
rising edge after PD goes high. The Power Down exit function is asynchronous operation.
designated by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the
next clock of the RDA command, the data is read out sequentially synchronizing with the both edges of DQS
output signal (Burst Read Operation). The initial valid read data appears after CAS latency from the issuing
of the LAL command. The valid data is outputted for a burst length. The CAS latency, the burst length of read
data and the burst type must be set in the Mode Register beforehand. The read operated bank goes back
automatically to the idle state after l
PD held “Low”. During Self-Refresh mode, all input and output buffers except for PD are disabled, therefore
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank
TC59LM814/06CTG are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun
It is the function of Self-Refresh operation that refresh operation can be performed automatically by using an
When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM814/06CTG become Power
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank
REFC
PD
. The Self-Refresh exit function is asynchronous operation. It is required that one
= “L”)
RC
.
RC
CKD
.
period. The device is in Self-Refresh mode as long as
TC59LM814/06CTG-50,-60
PD
2005-06-21 33/39
REFC
= “L”)
from Self-Refresh
REFC
REFC
Rev 1.2
. However,
period.
FPDL