tc59lm814 TOSHIBA Semiconductor CORPORATION, tc59lm814 Datasheet - Page 27

• Manufacturer Part Number: tc59lm814
• Description: 256mbits Network Fcram1
• Manufacturer: TOSHIBA Semiconductor CORPORATION

MODE REGISTER SET TIMING (CL = 3, BL = 2)
POWER DOWN TIMING (CL = 3, BL = 2)
Command
Command
BA0, BA1
Read cycle to Power Down Mode
A14~A0
(output)
(output)
(output)
(output)
DQS
CLK
DQS
CLK
CLK
CLK
DQ
DQ
PD
Note: “×” is don’t care
Hi-Z
Hi-Z
BA, UA
Hi-Z
Hi-Z
RDA
I
RDA
I
RCD
RCD
I
I
PD must be kept "High" level until end of Burst data output.
PD should be brought to high within t
0
PD
PDA
0
is defined from the first clock rising edge after PD is brought to “Low”.
= 1 cycle
= 1 cycle
is defined from the first clock rising edge after PD is brought to “High”.
LAL
LAL
LA
1
1
I
RC
2
2
CL = 3
CL = 3
= 5 cycles
I
RAS
DESL
3
= 4 cycles
3
×
DESL
4
4
Q0 Q1
Q0 Q1
REFI(max)
t
RDA
I
QPDH
RCD
5
5
Power Down Entry
t
IH
to maintain the data written into cell.
= 1 cycle
t
code)
MRS
IS
Valid
(op-
6
6
Hi-Z
Hi-Z
I
PD
= 1 cycle
l
TC59LM814/06CTG-50,-60
RC(min),
7
7
I
RSC
n − 1
t
REFI(max)
8
Hi-Z
Hi-Z
= 5 cycles
DESL
×
Power Down Exit
×
9
n
2005-06-21 27/39
t
PDEX
DESL
n + 1
I
10
PDA
= 1 cycle
BA, UA
WRA
RDA
WRA
n + 2
RDA
Rev 1.2
11
or
or