xr16v2550im Exar Corporation, xr16v2550im Datasheet - Page 22

• Manufacturer Part Number: xr16v2550im
• Description: High Performance Duart With 16-byte Fifo
• Manufacturer: Exar Corporation

XR16V2550
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
.
A
A2-A0
DDRESS
0 0 0
0 0 0
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0
0 0 0
0 0 1
T
ABLE
DREV
N
DVID
MCR
MSR
RHR
DLM
THR
FCR
LCR
SPR
DLD
R
LSR
DLL
IER
ISR
AME
EG
9: INTERNAL REGISTERS DESCRIPTION.
RD/WR
RD/WR Divisor
RD/WR
RD/WR
RD/WR
RD/WR
RD/WR
R
W
WR
WR
RD
RD
RD
RD
RD
RD
EAD
RITE
/
RX FIFO
RX FIFO
CTS Int.
Enabled
Enable
Trigger
Enable
Global
FIFOs
Pres-
B
BRG
caler
Error
Input
Bit-7
Bit-7
CD#
Bit-7
Bit-7
Bit-7
Bit-7
IT
0/
0/
0
0
-7
RI# Input
RX FIFO
IR Mode
RTS Int.
Enabled
Trigger
Enable
Set TX
Enable
THR &
FIFOs
Empty
Break
B
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
TSR
IT
0/
0/
0
0
-6
16C550 Compatible Registers
Baud Rate Generator Divisor
CTS INT
4X Mode 8X Mode
TX FIFO
XonAny
Xoff Int.
Enable
Trigger
Empty
Status
DSR#
Parity
B
RTS/
Input
Bit-5
Bit-5
THR
Bit-5
Bit-5
Bit-5
Bit-5
Set
IT
0/
0/
0/
0/
0
-5
22
TX FIFO
Xoff/Xon
Internal
Trigger
Enable
special
Enable
Break
Sleep
Mode
Parity
Loop-
CTS#
B
Even
Input
Bit-4
Bit-4
back
Bit-4
Bit-4
Bit-4
Bit-4
INT
RX
IT
0/
0/
0/
0
-4
S
HADED BITS ARE ENABLED WHEN
OP2#/INT
RX Fram-
ing Error
Stat. Int.
Modem
Source
Enable
Enable
Enable
Enable
Output
Mode
Parity
B
Delta
DMA
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
CD#
INT
IT
0
-3
RX Line
IR Input
(OP1#)
Enable
Source
Reset
Parity
Invert
B
FIFO
Delta
Error
Bit-2
Bit-2
Stat.
Bit-2
Stop
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
INT
Bits
RI#
Int.
RX
TX
IT
0
-2
Enable
Source
Control
Length
Output
Empty
Reset
DSR#
RTS#
Over-
B
FIFO
Word
Delta
Error
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
INT
RX
RX
run
TX
Int
IT
1
-1
EFR B
Source
Control
Enable
Enable
Length
Output
Ready
FIFOs
DTR#
CTS#
B
Word
Delta
Bit-0
Bit-0
Data
Bit-0
Bit-0
Data
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
INT
RX
Int.
RX
IT
0
-0
IT
-4=1
LCR ≠ 0xBF
LCR ≠ 0xBF
LCR ≠ 0xBF
LCR ≠ 0xBF
LCR ≠ 0xBF
EFR[4] = 1
DLM=0x00
DLL=0x00
C
LCR[7]=0
LCR[7]=1
LCR[7]=1
LCR[7]=1
REV. 1.0.2
OMMENT