xr16v2550im Exar Corporation, xr16v2550im Datasheet - Page 3

• Manufacturer Part Number: xr16v2550im
• Description: High Performance Duart With 16-byte Fifo
• Manufacturer: Exar Corporation

REV. 1.0.2
PIN DESCRIPTIONS
Pin Description
DATA BUS INTERFACE
RXRDYA#
TXRDYB#
TXRDYA#
N
IOW#
CSA#
CSB#
IOR#
INTB
INTA
D7
D6
D5
D4
D3
D2
D1
D0
A2
A1
A0
AME
32-QFN
P
18
19
20
32
31
30
29
28
27
14
12
22
21
IN
2
1
7
8
-
-
-
#
48-TQFP
P
26
27
28
48
47
46
45
44
19
15
10
30
29
43
31
IN
11
3
2
1
6
#
T
I/O
YPE
O
O
O
O
O
I
I
I
I
I
Address data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
Data bus lines [7:0] (bidirectional).
Input/Output Read Strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
UART channel A select (active low) to enable UART channel A in the
device for data bus operation.
UART channel B select (active low) to enable UART channel B in the
device for data bus operation.
UART channel A Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTA is set to the active
mode and OP2A# output LOW when MCR[3] is set to a logic 1. INTA is
set to the three state mode and OP2A# output HIGH when MCR[3] is
set to a logic 0 (default). See MCR[3].
UART channel B Interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTB is set to the active
mode and OP2B# output LOW when MCR[3] is set to a logic 1. INTB is
set to the three state mode and OP2B# output HIGH when MCR[3] is
set to a logic 0 (default). See MCR[3].
UART channel A Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel A. See
used, leave it unconnected.
UART channel A Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel A. See
used, leave it unconnected.
UART channel B Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel B. See
used, leave it unconnected.
3
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
D
ESCRIPTION
Table 2
Table 2
Table 3
XR16V2550
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