xr16v2550im Exar Corporation, xr16v2550im Datasheet - Page 33

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xr16v2550im

Manufacturer Part Number
xr16v2550im
Description
High Performance Duart With 16-byte Fifo
Manufacturer
Exar Corporation
Datasheet

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REV. 1.0.2
These registers make-up the value of the baud rate divisor. The concatenation of the contents of DLM and DLL
is a 16-bit value. Then the value is added to DLD[3:0]/16 to achieve the fractional baud rate divisor. DLD must
be enabled via EFR bit-4 before it can be accessed. See
Baud Rate Generator with Fractional Divisor” on page
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See
DLD[7:6]: Reserved
This register contains the device ID (0x02 for XR16V2550). Prior to reading this register, DLL and DLM should
be set to 0x00 (DLD = 0xXX).
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00 (DLD = 0xXX).
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
4.11
4.12
4.13
4.14
Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write
Device Identification Register (DVID) - Read Only
Device Revision Register (DREV) - Read Only
Enhanced Feature Register (EFR)
DLD[5]
0
0
1
T
ABLE
13: S
Table
AMPLING
DLD[4]
14). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
33
X
HIGH PERFORMANCE DUART WITH 16-BYTE FIFO
0
1
Table 13
10.
R
ATE
S
ELECT
below and
“Section 2.10, Programmable
Table 13
S
AMPLING
16X
8X
4X
XR16V2550
R
below.
ATE

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