sc16c2550b NXP Semiconductors, sc16c2550b Datasheet - Page 22

• Manufacturer Part Number: sc16c2550b
• Description: 5 V, 3.3 V And 2.5 V Dual Uart, 5 Mbit/s Max. , With 16-byte Fifos
• Manufacturer: NXP Semiconductors

NXP Semiconductors
SC16C2550B_4
Product data sheet
7.7 Line Status Register (LSR)
This register provides the status of data transfers between the SC16C2550B and
the CPU.
Table 19.
Bit
7
6
5
4
3
2
1
Symbol
LSR[7]
LSR[6]
LSR[5]
LSR[4]
LSR[3]
LSR[2]
LSR[1]
Line Status Register bits description
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Description
FIFO data error.
THR and TSR empty. This bit is the Transmit Empty indicator. This bit is set
to a logic 1 whenever the Transmit Holding Register and the Transmit Shift
Register are both empty. It is reset to logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode, this bit is set to ‘1’
whenever the Transmit FIFO and Transmit Shift Register are both empty.
THR empty. This bit is the Transmit Holding Register Empty indicator. This bit
indicates that the UART is ready to accept a new character for transmission.
In addition, this bit causes the UART to issue an interrupt to CPU when the
THR interrupt enable is set. The THR bit is set to a logic 1 when a character
is transferred from the transmit holding register into the transmitter shift
register. The bit is reset to a logic 0 concurrently with the loading of the
transmitter holding register by the CPU. In the FIFO mode, this bit is set
when the transmit FIFO is empty; it is cleared when at least 1 byte is written
to the transmit FIFO.
Break interrupt.
Framing error.
Parity error.
Overrun error.
Rev. 04 — 15 February 2007
logic 0 = no error (normal default condition)
logic 1 = at least one parity error, framing error or break indication is in the
current FIFO data. This bit is cleared when there are no remaining error
flags associated with the remaining data in the FIFO.
logic 0 = no break condition (normal default condition)
logic 1 = the receiver received a break signal (RX was a logic 0 for one
character frame time). In the FIFO mode, only one break character is
loaded into the FIFO.
logic 0 = no framing error (normal default condition)
logic 1 = framing error. The receive character did not have a valid stop
bit(s). In the FIFO mode, this error is associated with the character at the
top of the FIFO.
logic 0 = no parity error (normal default condition
logic 1 = parity error. The receive character does not have correct parity
information and is suspect. In the FIFO mode, this error is associated with
the character at the top of the FIFO.
logic 0 = no overrun error (normal default condition)
logic 1 = overrun error. A data overrun error occurred in the Receive Shift
Register. This happens when additional data arrives while the FIFO is full.
In this case, the previous data in the shift register is overwritten. Note that
under this condition, the data byte in the Receive Shift Register is not
transferred into the FIFO, therefore the data in the FIFO is not corrupted by
the error.
SC16C2550B
© NXP B.V. 2007. All rights reserved.
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