sc16c2550b NXP Semiconductors, sc16c2550b Datasheet - Page 41
sc16c2550b
Manufacturer Part Number
sc16c2550b
Description
5 V, 3.3 V And 2.5 V Dual Uart, 5 Mbit/s Max. , With 16-byte Fifos
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C2550B.pdf
(43 pages)
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NXP Semiconductors
13. Abbreviations
14. Revision history
Table 30.
SC16C2550B_4
Product data sheet
Document ID
SC16C2550B_4
Modifications:
SC16C2550B_3
SC16C2550B-02
(9397 750 14449)
Modifications:
SC16C2550B-01
(9397 750 11982)
Revision history
Release date
20070215
20050926
20041214
20050719
Table 29.
Acronym
CPU
DLL
DLM
DMA
FIFO
ISDN
LSB
MSB
RHR
THR
UART
•
•
•
•
•
The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
Legal texts have been adapted to the new company name where appropriate.
Section 2
Added
There is no modification to the data sheet. However, reader is advised to refer to
AN10333 (Rev. 02) “SC16CXXXB baud rate deviation tolerance” (9397 750 14411) that was
released together with this revision (-02).
Section 3.1 “Ordering options”
Abbreviations
“Features”: added (new) third bullet item
Data sheet status
Product data sheet
Product data sheet
Product data
Product data
Description
Central Processing Unit
Divisor Latch LSB
Divisor Latch MSB
Direct Memory Access
First In/First Out
Integrated Service Digital Network
Least Significant Bit
Most Significant Bit
Receive Holding Register
Transmit Holding Register
Universal Asynchronous Receiver/Transmitter
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Rev. 04 — 15 February 2007
Change notice
-
-
-
-
SC16C2550B
Supersedes
SC16C2550B_3
SC16C2550B-02
SC16C2550B-01
-
© NXP B.V. 2007. All rights reserved.
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