wm8918 Wolfson Microelectronics plc, wm8918 Datasheet - Page 103

• Manufacturer Part Number: wm8918
• Description: Ultra Low Power Dac For Portable Audio Applications
• Manufacturer: Wolfson Microelectronics plc

Production Data
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FREE-RUNNING FLL CLOCK
The FLL can generate a clock signal even when no external reference is available. However, it
should be noted that the accuracy of this clock is reduced, and a reference source should always be
used where possible. Note that, in free-running mode, the FLL is not sufficiently accurate for hi-fi
DAC applications. However, the free-running mode is suitable for clocking most other functions,
including the Write Sequencer, Charge Pump, DC Servo and Class W output driver.
If an accurate reference clock is available at FLL start-up, then the FLL should be configured as
described above. The FLL will continue to generate a stable output clock after the reference input is
stopped or disconnected.
If no reference clock is available at the time of starting up the FLL, then an internal clock frequency
of approximately 12MHz can be generated by enabling the FLL Analogue Oscillator using the
FLL_OSC_ENA register bit, and setting F
defined in Table 66. Under recommended operating conditions, the FLL output may be forced to
approximately 12MHz by then enabling the FLL_FRC_NCO bit and setting FLL_FRC_NCO_VAL to
19h (see Table 67). The resultant SYSCLK delivers the required clock frequencies for the Class W
output driver, DC Servo, Charge Pump and other functions. Note that the value of
FLL_FRC_NCO_VAL may be adjusted to control F
correct relationship between SYSCLK and the aforementioned functional blocks.
Table 67 FLL Free-Running Mode
In both cases described above, the FLL must be selected as the SYSCLK source by setting
SYSCLK_SRC (see Table 57). Note that, in the absence of any reference clock, the FLL output is
subject to a very wide tolerance. See “Electrical Characteristics” for details of the FLL accuracy.
GPIO OUTPUTS FROM FLL
The WM8918 has an internal signal which indicates whether the FLL Lock has been achieved. The
FLL Lock status is an input to the Interrupt control circuit and can be used to trigger an Interrupt
event - see “Interrupts”.
The FLL Lock signal can be output directly on a GPIO pin as an external indication of FLL Lock. See
“General Purpose Input/Output (GPIO)” for details of how to configure a GPIO pin to output the FLL
Lock signal.
The FLL Clock can be output directly on a GPIO pin as a clock signal for other circuits. Note that the
FLL Clock may be output even if the FLL is not selected as the WM8918 SYSCLK source. The
clocking configuration is illustrated in Figure 59. See “General Purpose Input/Output (GPIO)” for
details of how to configure a GPIO pin to output the FLL Clock.
R248 (F8h)
FLL NCO Test 1
R247 (F7h)
FLL NCO Test 0
REGISTER
ADDRESS
BIT
5:0
0
FLL_FRC_NCO
FLL_FRC_NCO
_VAL [5:0]
LABEL
OUT
clock divider to divide by 8 (FLL_OUTDIV = 07h), as
DEFAULT
01_1001
OUT
0
, but care should be taken to maintain the
FLL Forced oscillator value
Valid range is 000000 to 111111
0x19h (011001) = 12MHz approx
(Note that this field is required for
free-running FLL modes only)
FLL Forced control select
0 = Normal
1 = FLL oscillator controlled by
FLL_FRC_NCO_VAL
(Note that this field is required for
free-running FLL modes only)
PD, Rev 4.0, September 2010
DESCRIPTION
WM8918
103