wm8918 Wolfson Microelectronics plc, wm8918 Datasheet - Page 95

• Manufacturer Part Number: wm8918
• Description: Ultra Low Power Dac For Portable Audio Applications
• Manufacturer: Wolfson Microelectronics plc

Production Data
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SYSCLK CONTROL
The SYSCLK_SRC bit is used to select the source for SYSCLK. The source may be either the MCLK
input or the FLL output. The MCLK input can be inverted or non-inverted, as selected by the
MCLK_INV bit. The selected source may also be adjusted by the MCLK_DIV divider to generate
SYSCLK. These register fields are described in Table 57. See “Frequency Locked Loop (FLL)” for
more details of the Frequency Locked Loop clock generator.
The SYSCLK signal is enabled by register bit CLK_SYS_ENA. This bit should be set to 0 when
reconfiguring clock sources. It is not recommended to change SYSCLK_SRC while the
CLK_SYS_ENA bit is set.
The following operating frequency limits must be observed when configuring SYSCLK. Failure to
observe these limits will result in degraded noise performance and/or incorrect DMIC/DAC
functionality.
Note that DAC Mono mode (DAC_MONO = 1) is only valid when one or other DAC is disabled. If
both DACs are enabled, then the minimum SYSCLK for clocking the DACs is 128 x fs.
The SYSCLK control register fields are defined in Table 57.
Table 57 MCLK and SYSCLK Control
CONTROL INTERFACE CLOCKING
Register map access is possible with or without a Master Clock (MCLK). However, if CLK_SYS_ENA
has been set to 1, then a Master Clock must be present for control register Read/Write operations. If
CLK_SYS_ENA = 1 and MCLK is not present, then register access will be unsuccessful. (Note that
read/write access to register R22, containing CLK_SYS_ENA, is always possible.)
If it cannot be assured that MCLK is present when accessing the register map, then it is required to
set CLK_SYS_ENA = 0 to ensure correct operation.
It is possible to use the WM8918 analogue bypass paths to the differential line outputs (LON/LOP
and RON/ROP) without MCLK. Note that MCLK is always required when using HPOUTL, HPOUTR,
LINEOUTL or LINEOUTR.
R22 (16h)
Clock Rates
2
R20 (14h)
Clock Rates
0
REGISTER
ADDRESS





SYSCLK ≥ 3MHz
If DAC_OSR128 = 1 then SYSCLK ≥ 6MHz
If DAC_MONO = 1, then SYSCLK ≥ 64 x fs
If DAC_MONO = 0, then SYSCLK ≥ 128 x fs
If DMICL_ENA = 1 or DMICR_ENA = 1 then SYSCLK ≥ 256 x fs
BIT
15
14
2
0
CLK_SYS_ENA
SYSCLK_SRC
MCLK_INV
MCLK_DIV
LABEL
DEFAULT
0
0
0
0
MCLK Invert
0 = MCLK not inverted
1 = MCLK inverted
SYSCLK Source Select
0 = MCLK
1 = FLL output
System Clock enable
0 = Disabled
1 = Enabled
Enables divide by 2 on MCLK
0 = SYSCLK = MCLK
1 = SYSCLK = MCLK / 2
PD, Rev 4.0, September 2010
DESCRIPTION
WM8918
95