wm8215 Wolfson Microelectronics plc, wm8215 Datasheet - Page 19

• Manufacturer Part Number: wm8215
• Description: 60msps 10-bit 3-channel Ccd Digitiser
• Manufacturer: Wolfson Microelectronics plc

WM8215
CALCULATING THE OUTPUT CODE FOR A GIVEN INPUT
w
the WM8215.
INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING
If CDS = 1, (i.e. CDS operation) the previously sampled reset level, V
input video, V
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted
instead.
If VRLCDACPD = 1, V
If VRLCDACPD = 0, V
V
OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST
The resultant signal V
PGA NODE: GAIN ADJUST
The signal is then multiplied by the PGA gain.
ADC BLOCK: ANALOGUE-DIGITAL CONVERSION
The analogue signal is then converted to a 10-bit unsigned number, with input range configured by
PGAFS[1:0].
where the ADC full-scale range, V
OUTPUT INVERT BLOCK: POLARITY ADJUST
The polarity of the digital output may be inverted by control bit INVOP.
The following equations describe the processing of the video and reset level signals through
V
V
V
V
V
D
D
D
D
RLCSTEP
1
1
VRLC
2
3
1
1
2
2
[9:0] = INT{ (V
[9:0] = INT{ (V
[9:0] = D
[9:0] = 1023 – D
is the step size of the RLC DAC and V
=
=
=
=
=
1
[9:0]
IN
(= RINP, GINP or BINP).
3
3
/V
/V
1
[9:0]
V
V
(V
V
V
(INVOP = 0)
FS
FS
1
IN
IN
1
2
VRLC
VRLC
) ∗ 1023}
) ∗ 1023} + 1023
RLCSTEP
is added to the Offset DAC output.
+ {255mV ∗ (DAC[7:0]-127.5) } / 127.5
∗ (0.66 + PGA[8:0]x7.34/511)
- V
- V
RESET
VRLC
is an externally applied voltage on pin VRLC/VBIAS.
is the output from the internal RLC DAC.
∗ RLC DAC[3:0]) + V
(INVOP = 1)
FS
= 2V when LOWREFS=0 and V
RLCBOT
PGAFS[1:0] = 11
PGAFS[1:0] = 10
RLCBOT
is the minimum output of the RLC DAC.
FS
= 1.2V when LOWREFS=1.
RESET
PD, Rev 4.2, February 2009
, is subtracted from the
Eqn. 1
Eqn. 2
Eqn. 3
Eqn. 4
Eqn. 5
Eqn. 7
Eqn. 8
Eqn. 9
Eqn. 10
Production Data
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