wm8215 Wolfson Microelectronics plc, wm8215 Datasheet - Page 9

• Manufacturer Part Number: wm8215
• Description: 60msps 10-bit 3-channel Ccd Digitiser
• Manufacturer: Wolfson Microelectronics plc

WM8215
Figure 3 One-channel CDS Operation (CDS=1)
Notes:
1.
2.
3.
4.
5.
6.
7.
Test Conditions
AVDD = DVDD1 = DVDD2 = 3.3V, AGND = DGND = 0V, T
for 1-channel mode unless otherwise stated.
w
PARAMETER
MCLK period – 2/3 channel mode
MCLK high period – 2/3 channel mode
MCLK low period – 2/3 channel mode
RSMP pulse high time
VSMP pulse high time
RSMP falling to VSMP rising time
MCLK rising to VSMP rising time
MCLK falling to VSMP falling time
MCLK falling to VSMP falling time in 1
channel mode
VSMP falling to MCLK rising time
1
RSMP rising time
3-channel mode pixel period
2-channel mode pixel period
1-channel mode pixel period
st
MCLK falling edge after VSMP falling to
The relationship between input video signal and sample points is controlled by VSMP and RSMP.
When VSMP is high the input video signal is connected to the Video sampling capacitors.
When RSMP is high the input video signal is connected to the Reset sampling capacitors.
RSMP must not go high before the first falling edge of MCLK after VSMP goes low.
It is required that the falling edge of VSMP should occur before the rising edge of MCLK.
In 1-channel CDS mode it is not possible to have an equally spaced Video and Reset sample points with a 45MHz
MCLK.
Non-CDS operation is also possible; RSMP is not required in this mode but can be used to control input clamping.
Timing constraints between vsmp and mclk remain unchanged for non-CDS operation.
1 channel mode
1 channel mode
1 channel mode
SYMBOL
t
t
t
t
t
t
t
t
RSFVSR
MCLKH
MRVSR
VSFMR
MCLKL
MFVSF
MFVSF
MF1RS
t
t
t
t
t
t
PER
RSD
VSD
PR3
PR2
PR1
A
= 25°C, MCLK = 60MHz for 3 and 2-channel mode and 45MHz
TEST CONDITIONS
22.2
16.6
33.3
22.2
MIN
6.7
6.7
50
5
5
0
3
0
7
0
1
PD, Rev 4.2, February 2009
11.1
11.1
TYP
8.3
8.3
MAX
Production Data
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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