wm8215 Wolfson Microelectronics plc, wm8215 Datasheet - Page 25

• Manufacturer Part Number: wm8215
• Description: 60msps 10-bit 3-channel Ccd Digitiser
• Manufacturer: Wolfson Microelectronics plc

ADDRESS
000010
(02h)
000011
(03h)
000100
(04h)
000101
(05h)
000110
(06h)
WM8215
w
<A5:A0>
Setup Register
2
Setup Register
3
Software Reset
Auto-cycle
Reset
Setup Register
4
REGISTER
BIT
1:0
7:6
3:0
7:6
NO
2
3
4
5
4
5
0
RLCDACRNG
RLCDAC[3:0]
LINEBYLINE
LOWREFS
CHAN[1:0]
Not Used
Reserved
Reserved
NAME(S)
DEL[1:0]
INVOP
OPD
BIT
DEFAULT
1111
00
00
00
0
0
0
1
1
0
0
Must be set to 0
Digitally inverts the polarity of output data.
0 = negative going video gives negative going output,
1 = negative-going video gives positive going output data.
Output Disable. This works with the OEB pin to control the
output pins.
0=Digital outputs enabled, 1=Digital outputs high
impedance
OEB
(pin)
0
0
1
1
Reduces the ADC reference range (2*[VRT-VRB]), thus
changing the max/min input video voltages (ADC ref
range/PGA gain).
0 = ADC reference range = 2.0V
1 = ADC reference range = 1.2V
Sets the output range of the RLCDAC.
0 = RLCDAC ranges from 0 to AVDD (approximately),
1 = RLCDAC ranges from 0 to VRT (approximately).
Controls the latency from sample to data appearing on
output pins
DEL
00
01
10
11
Controls RLCDAC driving VRLC/VBIAS pin to define single
ended signal reference voltage or Reset Level Clamp
voltage. See Electrical Characteristics section for ranges.
Must be set to one
Must be set to zero
When MONO=0 this register bit has no effect
Monochrome mode channel select.
00 = Red
channel select
01 = Green
channel select
Any write to Software Reset causes all cells to be reset. It
is recommended that a software reset be performed after a
power-up before any other register writes.
Any write to Auto-cycle Reset causes the auto-cycle
counter to reset to RINP. This function is only required
when LINEBYLINE = 1.
Selects line by line operation. Line by line operation is
intended for use with systems which operate one line at a
time but with up to three colours shared on that one output.
0 = normal operation,
1 = line by line operation.
When line by line operation is selected MONO is forced to
1 and CHAN[1:0] to 00 internally, ensuring that the correct
internal timing signals are produced. Green and Blue PGAs
are also disabled to save power.
OPD
0
1
0
1
Latency
7 MCLK periods
8 MCLK periods
9 MCLK periods
10 MCLK periods
OP pins
Enabled
High Impedance
High Impedance
High Impedance
10 = Blue channel select
11 = Reserved
DESCRIPTION
PD, Rev 4.2, February 2009
Production Data
25