mt9075bpr1 Zarlink Semiconductor, mt9075bpr1 Datasheet - Page 14

• Manufacturer Part Number: mt9075bpr1
• Description: E1 Single Chip Transceiver With Liu
• Manufacturer: Zarlink Semiconductor

•
•
•
•
The PCM 30 Interface
PCM 30 (E1) basic frames are 256 bits long and are transmitted at a frame repetition rate of 8000 Hz, which
results in an aggregate bit rate of 256 bits x 8000/sec = 2.048 Mbits/sec. The actual bit rate is 2.048 Mbits/sec
+/-50 ppm encoded in HDB3 format. The HDB3 control bit (page 01H, address 15H, bit 5) selects either HDB3
encoding or alternate mark inversion (AMI) encoding. Basic frames are divided into 32 time slots numbered 0 to
31, see Figure 30. Each time slot is 8 bits in length and is transmitted most significant bit first (numbered bit 1). This
results in a single time slot data rate of 8 bits x 8000/sec. = 64 kbits/sec.
It should be noted that the Zarlink ST-BUS also has 32 channels numbered 0 to 31, but the most significant bit
of an eight bit channel is numbered bit 7 (see Zarlink Application Note MSAN-126). Therefore, ST-BUS bit 7 is
synonymous with PCM 30 bit 1; bit 6 with bit 2: and so on (Figure 31).
PCM 30 time slot 0 is reserved for basic frame alignment, CRC-4 multiframe alignment and the communication
of maintenance information. In most configurations time slot 16 is reserved for either Channel Associated Signalling
(CAS or ABCD bit signalling) or Common Channel Signalling (CCS). The remaining 30 time slots are called
channels and carry either PCM encoded voice signals or digital data. Channel alignment and bit numbering is
consistent with time slot alignment and bit numbering. However, channels are numbered 1 to 30 and relate to time
slots as per Table 3.
Basic Frame Alignment
Time slot 0 of every basic frame is reserved for basic frame alignment and contains either a Frame Alignment
Signal (FAS) or a Non-Frame Alignment Signal (NFAS). FAS and NFAS occur in time slot zero of consecutive basic
frames as shown in Table 7. Bit two is used to distinguish between FAS (bit two = 0) and NFAS (bit two = 1).
Basic frame alignment is initiated by a search for the bit sequence 0011011 which appears in the last seven bit
positions of the FAS, see the Frame Algorithm section. Bit position one of the FAS can be either a CRC-4 remainder
bit or an international usage bit.
Bits four to eight of the NFAS (i.e., S
•
•
In SysBusSync2 mode, the clock applied to pin C4b is assumed to be jitter-free and is directly used to
transmit data. The internal PLL is used to dejitter the extracted receive clock. The dejittered receive clock is
output on pin E2o.
In SysBusSync3 mode, no jitter attenuation is applied to either the transmit or receive clocks. The transmit
data is synchronized to clock applied to pin C4b. The extracted receive clock is not dejittered and is supplied
directly to the E2o output.
In Line Synchronous mode, the clock extracted from the receive data is dejittered using the internal PLL and
then output on pin C4b. Pin E2o provides the extracted receive clock before it has been dejittered. The
transmit data is synchronous to the clean receive clock.
In Free-Run mode the transmit data is synchronized to the internally generated clock. The internal clock is
output on pin C4b. The clock signal extracted from the receive data is not dejittered and is output directly on
pin E2o.
S
G.761).
S
a4
a4
to S
may be used as a message-based data link for operations, maintenance and performance monitoring.
a8
may be used in specific point-to-point applications (e.g. transcoder equipments conforming to
PCM 30
Timeslot
Voice/Data
Channels
Table 3 - Time Slot to Channel Relationship
a4
- S
a8
) are additional spare bits which may be used as follows:
0
x
Zarlink Semiconductor Inc.
MT9075B
1 2 3...15
1 2 3...15
14
16
x
17 18 19...31
16 17 18...30
Data Sheet