mt9075bpr1 Zarlink Semiconductor, mt9075bpr1 Datasheet - Page 78

• Manufacturer Part Number: mt9075bpr1
• Description: E1 Single Chip Transceiver With Liu
• Manufacturer: Zarlink Semiconductor

Bit
7-0
Bit
7
6
5
4
3
2
1
0
Ga, EOPD, TEOP,
EOPR, TxFl, FA:
Txunder, RxFf &
(000000)
RxOvfl
Seven
Name
Name
Rxfrst
Cycle
Txfrst
Intsel
Tcrci
RSV
RSV
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Table 90 - HDLC Interrupt Mask Register
This register is used with the Interrupt Register to mask out the interrupts
that are not required by the microprocessor. Interrupts that are masked out
will not produce an IRQ; however, they will set the appropriate bit in the
Interrupt Register. An interrupt is disabled when the microprocessor writes
a 0 to a bit in this register. This register is cleared on power reset.
Interrupt Selection. When one, this bit will cause bit 2 of the Interrupt
Register to reflect a TX FIFO underrun (TXunder). When zero, this
interrupt will reflect a frame abort (FA).
When one, this bit will cause the transmit byte count to cycle through the
value loaded into the Transmit Byte Count Register.
Transmit CRC Inhibited. When one, this bit will inhibit transmission of the
CRC. That is, the transmitter will not insert the computed CRC onto the bit
stream after seeing the EOP tag byte. This is used in V.120 terminal
adaptation for synchronous protocol sensitive UI frames.
Seven Bits Address Recognition. When one, this bit will enable seven
bits of address recognition in the first address byte. The received address
byte must have bit 0 equal to 1 which indicates a single address byte is
being received.
Reserved, must be zero for normal operation.
Reserved, must be zero for normal operation.
RX FIFO Reset. When one, the RX FIFO will be reset. This causes the
receiver to be disabled until the next reception of a flag. The status register
will identify the FIFO as being empty. However, the actual bit values in the
RX FIFO will not be reset.
TX FIFO Reset. When one, the TX FIFO will be reset. The Status Register
will identify the FIFO as being empty. This bit will be reset when data is
written to the TX FIFO. However, the actual bit values of data in the TX
FIFO will not be reset. It is cleared by the next write to the TX FIFO.
Table 89 - HDLC Control Register 2
(Pages 0BH & 0CH, Address 15H)
(Pages 0BH & 0CH, Address 16H)
Zarlink Semiconductor Inc.
MT9075B
78
Functional Description
Functional Description
Data Sheet