mt9075bpr1 Zarlink Semiconductor, mt9075bpr1 Datasheet - Page 76

• Manufacturer Part Number: mt9075bpr1
• Description: E1 Single Chip Transceiver With Liu
• Manufacturer: Zarlink Semiconductor

5, 4
3, 2
Bit
7
6
Txstat2, Txstat1
RQ9, RQ8
Idle Chan
Name
Intgen
Interrupt Generation. Intgen is set to 1 when an interrupt (in conjunction
with the Interrupt Mask Register) has been generated by the HDLC. This
is an asynchronous event. It is reset when the Interrupt Register is read.
Idle Channel. This bit is set to a 1 when an idle Channel state (15 or
more ones) has been detected at the receiver. This is an asynchronous
event. Status becomes valid after the first 15 bits or the first zero is
received.
Byte Status bits from RX FIFO. These bits determine the status of the
byte to be read from RX FIFO as follows:
Transmit Status. These bits indicate the status of the TX FIFO as
follows:
Table 88 - HDLC Status Register
(Pages 0BH & 0CH, Address 14H)
Txstat2
RQ9
0
0
1
1
0
0
1
1
Zarlink Semiconductor Inc.
MT9075B
76
Txstat1
RQ8
0
1
0
1
0
1
0
1
Functional Description
Packet byte.
First byte.
Last byte of a good packet.
Last byte of a bad packet.
TX FIFO full up to the selected status level
or more. See Table 93.
The number of bytes in the TX FIFO has
reached or exceeded the selected interrupt
threshold level. See Table 94.
TX FIFO empty.
The number of bytes in the TX FIFO is less
than the selected interrupt threshold level.
See Table 94.
TX FIFO Status
Byte Status
Data Sheet