mt9075bpr1 Zarlink Semiconductor, mt9075bpr1 Datasheet - Page 15

• Manufacturer Part Number: mt9075bpr1
• Description: E1 Single Chip Transceiver With Liu
• Manufacturer: Zarlink Semiconductor

MT9075B
Data Sheet
•
S
to S
are for national usage.
a5
a8
A maintenance channel or data link at 4,8,12,16,or 20 kHz for selected S
bits is provided by the MT9075B to
a
implement these functions. Note that for simplicity all S
bits including S
are collectively called national bits
a
a4
throughout this document.
Bit three (designated as “A”), the Remote Alarm Indication (RAI), is used to indicate the near end basic frame
synchronization status to the far end of a link. Under normal operation, the A (RAI) bit should be set to 0, while in
alarm condition, it is set to 1.
Bit position one of the NFAS can be either a CRC-4 multiframe alignment signal, an E-bit or an international usage
bit. Refer to an approvals laboratory and national standards bodies for specific requirements.
CRC-4 Multiframing
The primary purpose for CRC-4 multiframing is to provide a verification of the current basic frame alignment,
although it can also be used for other functions such as bit error rate estimation. The CRC-4 multiframe consists of
16 basic frames numbered 0 to 15, and has a repetition rate of 16 frames X 125 microseconds/frame = 2 msec.
CRC-4 multiframe alignment is based on the 001011 bit sequence, which appears in bit position one of the first six
NFASs of a CRC-4 multiframe.
The CRC-4 multiframe is divided into two submultiframes, numbered 1 and 2, which are each eight basic frames or
2048 bits in length.
The CRC-4 frame alignment verification functions as follows. Initially, the CRC-4 operation must be activated
and CRC-4 multiframe alignment must be achieved at both ends of the link. At the local end of a link, all the bits
4
4
of every transmit submultiframe are passed through a CRC-4 polynomial (multiplied by X
then divided by X
+
X + 1), which generates a four bit remainder. This remainder is inserted in bit position one of the four FASs of
the following submultiframe before it is transmitted (see Table 7).
The submultiframe is then transmitted and, at the far end, the same process occurs. That is, a CRC-4 remainder is
generated for each received submultiframe. These bits are compared with the bits received in position one of the
four FASs of the next received submultiframe. This process takes place in both directions of transmission.
When more than 914 CRC-4 errors (out of a possible 1000) are counted in a one second interval, the framing
algorithm will force a search for a new basic frame alignment. See Frame Algorithm section for more details.
The result of the comparison of the received CRC-4 remainder with the locally generated remainder will be
transported to the far end by the E-bits. Therefore, if E
= 0, a CRC-4 error was discovered in a submultiframe 1
1
received at the far end; and if E
= 0, a CRC-4 error was discovered in a submultiframe 2 received at the far end.
2
No submultiframe sequence numbers or re-transmission capabilities are supported with layer 1 PCM 30 protocol.
See ITU-T G.704 and G.706 for more details on the operation of CRC-4 and E-bits.
There are two CRC multiframe alignment algorithm options selected by the AUTC control bit (address 11H, page
01H). When AUTC is zero and CSYN is zero, automatic CRC-to-non-CRC interworking is selected, if CRC-4
multiframe alignment is not found in 400 msec, the status bit CRCIWK (page 03H, address 10H) is set low and no
further attempt to achieve CRC-4 synchronization is made as long as the device remains in terminal frame
synchronization. When AUTC is one and CSYN is zero, a reframe will be initiated every 8 msec if the MT9075B
achieves terminal frame synchronization, but fails to achieve CRC-4 synchronization. In this case, if ARAI is low,
RAI will flicker high with every reframe. If CRC MFAI is unsuccessful after 400ms, RAI will stay high continuously.
The control bit for transmit E bits (TE, bit 4 at address 16H of page 01H) will have the same function in both states
of AUTC. That is, when CRC-4 synchronization is not achieved the state of the transmit E-bits will be the same as
the state of the TE control bit. When CRC-4 synchronization is achieved the transmit E-bits will function as per ITU-
T G.704. Table 4 outlines the operation of the AUTC, ARAI and TALM control bits of the MT9075B.
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