mt9075bpr1 Zarlink Semiconductor, mt9075bpr1 Datasheet - Page 31

• Manufacturer Part Number: mt9075bpr1
• Description: E1 Single Chip Transceiver With Liu
• Manufacturer: Zarlink Semiconductor

MT9075B
Data Sheet
The overflow reporting latch (page 04H, address 16H) contains a register whose bits are set when individual
counters overflow. These bits stay high until the register is read.
PRBS Error Counter (PS7-0)
There are two 8 bit counters associated with PRBS comparison; one for errors and one for time. Any errors that are
detected in the receive PRBS will increment the PRBS Error Rate Counter of page 04H, address 10H. Writes to this
counter will clear an 8 bit counter, PSM7-0 (page 01H, address 11H) which counts receive CRC-4 multiframes. A
maskable PRBS counter overflow (PRBSO) interrupt (page 1, address 19H) is associated with this counter.
CRC Multiframe Counter for PRBS (PSM7-0)
This eight bit counter counts receive CRC-4 multiframes. It can be directly loaded via the microport. The counter will
also be automatically cleared in the event that the PRBS error counter is written to by the microport. This counter is
located on page 04H, address 11H.
E-bit Counter (EC9-0)
E-bit errors are counted by the MT9075B in order to support compliance with ITU-T requirements. This ten bit
counter is located on page 04H, addresses 13H and 14H respectively. It is incremented by single error events, with
a maximum rate of twice per CRC-4 multiframe.
There are two maskable interrupts associated with the E-bit error measurement. EBI (page 1, address 1CH) is
initiated when the least significant bit of the counter toggles, and EBO (page 01H, address 1DH) is initiated when
the counter overflows.
Jitter FIFO Counter (JFC7-0)
This is an eight bit counter that is incremented when the FIFO read pointer comes within 4 words of an underflow or
overflow condition. During this time the read clock will abruptly speed-up or slow-down to avoid an overflow or
underflow condition. This counter is located on page 04H, address 15H.
Loss of Synchronization Counter (LBF7-0)
This eight bit counter increments with each loss of basic frame alignment. This programmable counter is located on
page 04H, address 17H.
Bit Error Rate Counter (BR7-BR0)
An 8 bit Error Rate (BERT) counter BR7 - BR0 is located on page 04H address 18H, and is incremented once for
every bit detected in error on either the seven frame alignment signal bits.
There are two maskable interrupts associated with the bit error rate measurement. BERI (page 01H, address 1CH)
is initiated when the least significant bit of the BERT counter (BR0) toggles, and BERO (page 01H, address 1DH) is
initiated when the BERT counter value changes from FFH to 00H.
Errored FAS Counter (EFAS7-EFAS0)
An eight bit Frame Alignment Signal Error counter EFAS7 - EFAS0 is located on page 04H address 1AH, and is
incremented once for every receive frame alignment signal that contains one or more errors.
There are two maskable interrupts associated with the frame alignment signal error measurement. FERI (page
01H, address 1BH) is initiated when the least significant bit of the errored frame alignment signal counter toggles,
and FERO (page 01H, address 1DH) is initiated when the counter changes from FFH to 00H.
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