mt9075bpr1 Zarlink Semiconductor, mt9075bpr1 Datasheet - Page 16

• Manufacturer Part Number: mt9075bpr1
• Description: E1 Single Chip Transceiver With Liu
• Manufacturer: Zarlink Semiconductor

CAS Signalling Multiframing
The purpose of the signalling multiframing algorithm is to provide a scheme that will allow the association of a
specific ABCD signalling nibble with the appropriate PCM 30 channel. Time slot 16 is reserved for the
communication of Channel Associated Signalling (CAS) information (i.e., ABCD signalling bits for up to 30
channels). Refer to ITU-T G.704 and G.732 for more details on CAS multiframing requirements.
A CAS signalling multiframe consists of 16 basic frames (numbered 0 to 15), which results in a multiframe repetition
rate of 2 msec. It should be noted that the boundaries of the signalling multiframe may be completely distinct from
those of the CRC-4 multiframe. CAS multiframe alignment is based on a multiframe alignment signal (a 0000 bit
sequence), which occurs in the most significant nibble of time slot 16 of basic frame 0 of the CAS multiframe. Bit 6
of this time slot is the multiframe alarm bit (usually designated Y). When CAS multiframing is acquired on the
receive side, the transmit Y-bit is zero; when CAS multiframing is not acquired, the transmit Y-bit is one. Bits 5, 7
and 8 (usually designated X) are spare bits and are normally set to one if not used.
Time slot 16 of the remaining 15 basic frames of the CAS multiframe (i.e., basic frames 1 to 15) are reserved for the
ABCD signalling bits for the 30 payload channels. The most significant nibbles are reserved for channels 1 to 15
and the least significant nibbles are reserved for channels 16 to 30. That is, time slot 16 of basic frame 1 has ABCD
for channel 1 and 16, time slot 16 of basic frame 2 has ABCD for channel 2 and 17, through to time slot 16 of basic
frame 15 has ABCD for channel 15 and 30.
AUTC
0
0
0
1
1
1
ARAI
0
1
1
0
1
1
Table 4 - Operation of AUTC, ARAI and TALM Control Bits
TALM
x
0
1
x
0
1
Automatic CRC-interworking is activated. If no valid CRC MFAS is
being received, transmit RAI will flicker high with every reframe (8
msec.), this cycle will continue for 400 msec., then transmit RAI will be
low continuously. The device will stop searching for CRC MFAS,
continue to transmit CRC-4 remainders, stop CRC-4 processing
indicate CRC-to-non-CRC operation and transmit E-bits to be the same
state as the TE control bit (page 01H, address 16H).
Automatic CRC-interworking is activated. Transmit RAI is low
continuously upon loss of synchronization.
Automatic CRC-interworking is activated. Transmit RAI is high
continuously upon loss of synchronization.
Automatic CRC-interworking is de-activated. If no valid CRC MFAS is
being received, transmit RAI flickers high with every reframe (8 msec.),
this cycle continues for 400 msec., then transmit RAI becomes high
continuously. The device continues to search for CRC MFAS and
transmit E-bits are the same state as the TE control bit. When CRCSYN
= 0, the CRC MFAS search is terminated and the transmit RAI goes
low.
Automatic CRC-interworking is de-activated. Transmit RAI is low
continuously upon loss of synchronization.
Automatic CRC-interworking is de-activated. Transmit RAI is high
continuously upon loss of synchronization.
Zarlink Semiconductor Inc.
MT9075B
16
Description
Data Sheet