mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 101

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

5.2
The location of the absolute starting and ending addresses of the internal and external memories are shown in
Table 34 - MT90503 Memory Map. The complete set of internal registers is listed in section 5.5 "Detailed Register
Description", on Page 99.
5.3
Two memory controllers for external SSRAM exist in the MT90503: one for data memory and one for control
memory. The memory controller blocks of the MT90503 reside between the internal blocks and the external
memory. They receive memory access requests from the internal blocks (TDM, TX_SAR, RX_SAR, and CPU
interface modules) and service them by reading data from, or writing data to, the external memories.
5.3.1
The data memory contains
•
TX/RX circular buffers: one per channel, each with a programmable size of 128, 256, 512, or 1024 words.
Start Address
Memory Map
Memory Controllers
Data Memory
200000h
400000h
0A00h
1C00h
0100h
0200h
0300h
0400h
0500h
0600h
0700h
0800h
0900h
1000h
1400h
1800h
2000h
3000h
4000h
5000h
8000h
End Address
2FFFFEh
7FFFFEh
1CFEh
BFFEh
0AFEh
01FEh
02FEh
03FEh
04FEh
05FEh
06FEh
07FEh
08FEh
09FEh
10FEh
14FEh
18FEh
27FEh
33FEh
43FEh
53FEh
Table 34 - MT90503 Memory Map
Zarlink Semiconductor Inc.
MT90503
101
RX_SAR Registers
Miscellaneous Registers
H.100 Registers
RX SAR Output FIFO
External Control Memory
CPU Registers
Main Registers
UTOPIA Registers
TDM Registers
TX_SAR Registers
Scheduler Registers
Clock Registers
TX SAR Input FIFO
UTOPIA Port A Input FIFO
UTOPIA Port B Input FIFO
UTOPIA Port C Input FIFO
UTOPIA Port A Output FIFO
UTOPIA Port B Output FIFO
UTOPIA Port C Output FIFO
TDM Channel Association Memory
External Data Memory
Name
Data Sheet