mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 183

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Address: 886h
Label: diviclk0_reg3
Reset Value: 0000h
diviclk0_freq_too_high_pulse_genloss
Address: 888h
Label: diviclk0_reg4
Reset Value: 0063h
diviclk0_freq_too_low_pulse_genloss
diviclk0_ext_loss_source_polarity
diviclk0_freq_too_high_flag_genloss
diviclk0_freq_too_low_flag_genloss
diviclk0_ext_loss_source_select
diviclk0_ext_loss_pulse_genloss
diviclk0_output_loss_polarity
diviclk0_ext_loss_flag_genloss
reserved
Label
reserved
Label
Table 231 - Integer Clock Divisor0 3 Register
Table 232 - Integer Clock Divisor0 4 Register
Position
15:8
Bit
5:0
Position
6
7
15:6
Bit
0
1
2
3
4
5
Zarlink Semiconductor Inc.
MT90503
Type
RW
RW
RW
RW
Type
RW
RW
RW
RW
RW
RW
RW
183
Select's which external pin will signal that the input of
the integer clock divisor is good or not. See Table 28
- "Source Selection" on page 89 for more details.
Input of the integer clock divisor is considered bad
when the select ext_loss signal is active (i.e. equal to
this bit). 0 = source loss active low; 1 = source loss
active high.
When a loss is detected, the output signal indicating
this loss is activated (i.e. the value is this register is
sent out). '0' = output loss active low; '1' = output loss
active high.
Reserved. Must always be "0000_0000"
When set, the corresponding status will cause a
loss to be signaled for this diviclk.
When set, the corresponding status will cause a
loss to be signaled for this diviclk.
When set, the corresponding status will cause a
loss to be signaled for this diviclk.
When set, the corresponding status will cause a
loss to be signaled for this diviclk.
When set, the corresponding status will cause a
loss to be signaled for this diviclk.
When set, the corresponding status will cause a
loss to be signaled for this diviclk.
Reserved. Must always be "0000_0000_00"
Description
Description
Data Sheet