mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 39

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

However, when operating the CPU interface in direct mode with an 8-bit data bus bits, [19:15] are used for the lower
address word.
4.1.2.5
4.1.2.6
4.1.3
The following reset procedure is required to power-up the MT90503. The reset procedure must be adhered at
power-up employing the reset pin. Post power-up, the reset procedure can be performed from step 3.
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Write the upper address, extended_a[32:20], to register 0008h. This write may be not be required if previous
value holds true.
Write the lower address extended_a[19:16] or [19:15] to register 000Ah. The remaining bits [15:4] or [14:4]
are ignored. This write may be not be required if previous value holds true.
Write write_enable[13:12] (where applicable) and extended_parity[15:14]. The extended parity write is
optional.
Write the data value to the address within the corresponding memory page with the INMO_A_DAS bit set.
Write the upper address, extended_a[32:20], to register 0008h. This write may be not be required if previous
value holds true.
Write the lower address, extended_a[19:16] or [19:15], to register 000Ah. The remaining bits [15:4] or [14:4]
are ignored. This write may be not be required if previous value holds true.
Assert the lower address within the memory page and fetch the read data with INMO_A_DAS set.
An optional read may be performed to obtain the parity values, extended_parity[15:14] register 0000h.
Assert the reset pin for at least 1000 MCLK cycles.
De-assert the reset pin. All accesses in the remaining reset procedure will employ indirection.
Initialise the mem_clk_* bits and write_cache_enable bit via the Control Register bits [13:10],
address 0100h.
Write the mclk_src frequency at register led1[6:0] and LED Flash Frequency at registers led1[15:7],
register address 0120h. Write the LED Flash Frequency units (i.e. ms or s) at register led2[0], address
0122h.
Initialise the PLL via register pll_conf, address 0128h.
Set bits nreset_* in the Control Register bits [7:0], address 0100h.
Initialize the data and control memory types via registers 0240h, 0242h, 0244h, 0248h, 024Ah, and 024Ch
Select UTOPIA clocking methodology at register addresses 0230h, 0232h, 0234h and 0236h.
Configure the interrupts’ active_level for interrupt1 and interrupt2 in register 0224h and 0226h.
MT90503 Reset Procedure
Extended Direct Writes
Extended Direct Reads
Zarlink Semiconductor Inc.
MT90503
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Data Sheet