mt90503 Zarlink Semiconductor, mt90503 Datasheet - Page 46

• Manufacturer Part Number: mt90503
• Description: 2048vc Aal1 Sar
• Manufacturer: Zarlink Semiconductor

23. Subsequently, each time that a byte is written to the circular buffer, the offset field is read, and an offset is
established between the internal TDM pointer and the pointer that will be used.
The channel association structure for multiframe channels is slightly different, with only one bit being positioned
differently in the structure. While the circular buffer address and size field is still present and functions in the same
way, the mode bits are coded in the same way as they are in the transmit structure for multiframe channels. “0100”
is E1, “0110” is T1, and toggling the lowest bit of either of the numbers indicates that the FASTCAS method of
transmitting the data and CAS bytes are employed.
Four new fields are added to allow for CAS management on the RX side with multiframing:
•
•
•
•
Last RX CAS value that indicates the previous CAS bits received on ATM
The CAS monitor bit indicates if a change in the value of CAS is to be reported by the module
Man RX CAS is the value of CAS that can be inserted in the place of the one received. This value is only
used if the ME bit is set
ME bit Manual CAS insert
TX/RX Circular Buffer Address and Size : Address and size of the circular buffer in the data memory
from which data bytes will be
read
OE: Voice Stream Output Enable. This bit, when set, enables the driving of the Voice Data on the even
stream.
Mode: Channel Mode of operation.
C : Cut VC Status Enable. When ‘0’, the UR Count field is freerunning(256 consecutive underruns will
be cosidered as a Cut VC). When ‘1’, the UR Count field is used as a consecutive underrun indicator
stops incrementing at 255.
th t
U: Underrun Status Enable. When this bit is set and an underrun is detected, the status counters and
bits will report this
event
CU: CAS Underrun Enable. When this bit is set and an CAS underrun is detected, the status counters
UR Count : 8 bit underrun count. When the C bit is cleared, acts as a freerunning underrun error counter.
When the C bit is set, it is used as a cut VC detector. In this mode, the counter is cleared each time a
valid byte is received. It increments (to a maximum of FFh) each time a byte underrun is detected. When
a transition from FEh to FFh occurs, the Cut VC status register, counter and id fields are updated. Must
software
before enabling VC when C bit is cleared.
CM: CAS Monitor. When ‘1’, any change in RX CAS value will be reported to the CPU. When an
underrun occurs, a CAS change will never be reported.
CO: CAS Output Enable. This bit, when set, enables the driving of the CAS value out on the associated
odd TDM steam.
Last RX CAS : This is the value of the last RX CAS sent on the TDM bus. This value is not written if an
underrun has occured for this CAS value,
ME : Manual CAS Insert. When ‘1’, the Man RX CAS is sent instead of the CAS contained in the
memory.
Man RX CAS : CAS Value that is sent onto the TDM bus if ME = ‘1’.
and bits will report this
be initialized to FFh by software before enabling VC when C bit is set. Must be initialized to 00h by
t
“0100”=E1 Strict Multiframing;
“0101”=E1 FASTCAS;
“0110”=T1 Strict Multiframing;
“0111”=T1 FASTCAS;
others=Reserved.
l
Figure 12 - TDM Channel Association: RX Channels (CAS mode)
+0
+2
+4
+6
b15
b14
Mode
b13
TX/RX Circular Buffer Address and Size
b12
b11
C
b10
U
Zarlink Semiconductor Inc.
b9
0
b8
MT90503
1
0
b7
Man RX CAS ME
46
b6
b5
UR Count
b4
b3
Last RX CAS
CM
b2
CU
b1
OE
CO
b0
Reserved
Data Sheet