am79c961a Advanced Micro Devices, am79c961a Datasheet - Page 107

• Manufacturer Part Number: am79c961a
• Description: Pcnet?-isa Ii Jumperless, Full Duplex Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

11-0
CSR42-43: Current Transmit Status and Byte
Bit
31-24 CXST
23-12
11-0
CSR44-45: Next Receive Status and Byte Count
Bit
31-24 NRST
23-12
11-0
CSR46: Poll Time Counter
Bit
15-0
CRBC
CXBC
NRBC
POLL
Name
Name
Name
RES
RES
Count
Current Receive Byte Count.
This field is a copy of the BCNT
field of RMD2 of the current
receive descriptor.
Read/write
when STOP or SPND bits are
set.
Current Transmit Status. This
field is a copy of bits 15:8 of
TMD1 of the current transmit
descriptor.
Read/write accessible only when
STOP or SPND bits are set.
Reserved locations. Written as
zero and read as undefined.
Current Transmit Byte Count.
This field is a copy of the BCNT
field of TMD2 of the current
transmit descriptor.
Read/write accessible only when
STOP or SPND bits are set.
Next Receive Status. This field
is a copy of bits 15:8 of RMD1 of
the next receive descriptor.
Read/write accessible only when
STOP or SPND bits are set.
Reserved locations. Written as
zero and read as undefined.
Next Receive Byte Count. This
field is a copy of the BCNT field
of RMD2 of the next receive
descriptor.
Read/write accessible only when
STOP or SPND bits are set.
Poll Time Counter. This counter
is incriminated by the PCnet-ISA
II controller microcode and is
used to trigger the descriptor
ring polling operation of the PC-
net-ISA II controller.
Read/write accessible only when
STOP or SPND bits are set.
Description
Description
Description
accessible
only
Am79C961A
CSR47: Polling Interval
Bit
31-16
15-0 POLLINT
CSR48-49: Temporary Storage
Bit
31-0
CSR50-51: Temporary Storage
Bit
31-0
TMP0
TMP1
Name
Name
Name
RES
Reserved locations. Written as
zero and read as undefined.
Polling Interval. This register
contains the time that the PC-
net-ISA II controller will wait be-
tween
operations. The POLLINT value
is expressed as the two’s com-
plement of the desired interval,
where each bit of POLLINT rep-
resents one-half of an XTAL1
period of time. POLLINT[3:0] are
ignored. (POLINT[16] is implied
to be a one, so POLLINT[15] is
significant, and does not repre-
sent the sign of the two’s
complement POLLINT value.)
The default value of this register
is 0000. This corresponds to a
polling interval of 32,768 XTAL1
periods. The POLINT value of
0000 is created during the micro-
code initialization routine, and
therefore might not be seen when
reading CSR47 after RESET.
If the user desires to program a
value for POLLINT other than
the default, then the correct
procedure is to first set INIT only
in CSR0. Then, when the initial-
ization sequence is complete,
the user must set STOP in
CSR0. Then the user may write
to CSR47 and then set STRT in
CSR0. In this way, the default
value of 0000 in CSR47 will be
overwritten with the desired user
value.
Read/write
when STOP or SPND bits are
set.
Temporary Storage location.
Read/write
when STOP or SPND bits are
set.
Temporary Storage location.
successive
Description
Description
Description
accessible
accessible
polling
only
only
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