am79c961a Advanced Micro Devices, am79c961a Datasheet - Page 85

• Manufacturer Part Number: am79c961a
• Description: Pcnet?-isa Ii Jumperless, Full Duplex Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

with the Permanent Master driving AEN LOW, driving
the addressess valid, and driving IOR active. The
PCnet-ISA II controller detects this combination of sig-
nals and arbitrates for the Private Data Bus (PRDB) if
necessary. IOCHRDY is driven LOW during accesses
to the address PROM.
When the Private Data Bus becomes available, the
PCnet-ISA II controller drives APCS active, releases
IOCHRDY, turns on the data path from PRD0-7, and
enables the SD0-7 drivers (but not SD8-15). During
this bus cycle, IOCS16 is not driven active. This condi-
tion is maintained until IOR goes inactive, at which time
the bus cycle ends. Data is removed from SD0-7 within
30 ns.
Address PROM Cycles Using EEPROM Data
Default mode. In this mode, the IEEE address informa-
tion is stored not in an external parallel PROM but in the
EEPROM along with other configuration information.
PCnet-ISA II will respond to I/O reads from the IEEE
address (the first 16 bytes of the I/O map) by supplying
data from an internal RAM inside PCnet-ISA II. This in-
ternal RAM is loaded with the IEEE address at RESET
and is write protected.
Ethernet Controller Register Cycles
Ethernet controller registers (RAP, RDP, IDP) are natu-
rally 16-bit resources but can be configured to operate
with 8-bit bus cycles provided the proper protocol is fol-
lowed. This means on a read, the PCnet-ISA II control-
ler will only drive the low byte of the system data bus; if
an odd byte is accessed, it will be swapped down. The
high byte of the system data bus is never driven by the
PCnet-ISA II controller under these conditions. On a
write cycle, the even byte is placed in a holding register.
An odd byte write is internally swapped up and aug-
mented with the even byte in the holding register to pro-
vide an internal 16-bit write. This allows the use of 8-bit
I/O bus cycles which are more likely to be compatible
with all ISA-compatible clones, but requires that both
bytes be written in immediate succession. This is
accomplished simply by treating the PCnet-ISA II con-
troller registers as 16-bit software resources. The
motherboard will convert the 16-bit accesses done by
software into two sequential 8-bit accesses, an even
byte access followed immediately by an odd byte
access.
An access cycle begins with the Permanent Master
driving AEN LOW, driving the address valid, and driving
IOR or IOW active. The PCnet-ISA II controller detects
this combination of signals and drives IOCHRDY LOW.
IOCS16 will also be driven LOW if 16-bit I/O bus cycles
are enabled. When the register data is ready,
IOCHRDY will be released HIGH. This condition is
maintained until IOR or IOW goes inactive, at which
time the bus cycle ends.
Am79C961A
RESET Cycles
A read to the reset address causes an PCnet-ISA II
controller reset. This has the same effect as asserting
the RESET pin on the PCnet-ISA
happens on system power up or on a hard boot) except
that the T-MAU is NOT reset. The T-MAU will retain its
link pass/fail state, disregarding the software RESET
command. The subsequent write cycle needed in the
NE2100 LANCE based family of Ethernet cards is not
required but does not have any harmful effects.
IOCS16 is not asserted in this cycle.
ISA Configuration Register Cycles
The ISA configuration registers are accessed by plac-
ing the address of the desired register into the RAP and
reading the IDP. The ISACSR bus cycles are identical
to all other PCnet-ISA II controller register bus cycles.
Boot PROM Cycles
The Boot PROM is an 8-bit PROM connected to the
PCnet-ISA II controller Private Data Bus (PRDB) and
can occupy up to 64K of address space. Since the PC-
net-ISA II controller does not generate MEMCS16, only
8-bit ISA memory bus cycles to the boot PROM are
supported in Bus Master Mode; this limitation is trans-
parent to software and does not preclude 16-bit soft-
ware memory accesses. A boot PROM access cycle
begins with the Per manent Master driving the
addresses valid, REF inactive, and MEMR active. (AEN
is not involved in memory cycles). The PCnet-ISA II
controller detects this combination of signals, drives
IOCHRDY LOW, and reads a byte out of the Boot
PROM. The data byte read is driven onto the lower sys-
tem data bus lines and IOCHRDY is released. This
condition is maintained until MEMR goes inactive, at
which time the access cycle ends.
The BPCS signal generated by the PCnet-ISA II con-
troller is three 20 MHz clock cycles wide (300 ns).
Including delays, the Boot PROM has 275 ns to
respond to the BPCS signal from the PCnet-ISA II con-
troller. This signal is intended to be connected to the
CS pin on the boot PROM, with the PROM OE pin tied
to ground.
Current Master Operation
Current Master operation only occurs in the Bus Master
mode. It does not occur in the Bus Slave mode.
There are three phases to the use of the bus by the PC-
net-ISA II controller as Current Master, the Obtain
Phase, the Access Phase, and the Release Phase.
Obtain Phase
A Master Mode Transfer Cycle begins by asserting
DRQ. When the Permanent Master asserts DACK, the
PCnet-ISA II controller asserts MASTER, signifying it
has taken control of the ISA bus. The Permanent Mas-
ter tristates the address, command, and data lines
+
controller (which
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