am79c961a Advanced Micro Devices, am79c961a Datasheet - Page 146

no-image

am79c961a

Manufacturer Part Number
am79c961a
Description
Pcnet?-isa Ii Jumperless, Full Duplex Single-chip Ethernet Controller For Isa
Manufacturer
Advanced Micro Devices
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
am79c961aKC
Manufacturer:
AMD
Quantity:
220
Part Number:
am79c961aKC
Manufacturer:
LT
Quantity:
47
Part Number:
am79c961aKC
Manufacturer:
AMD
Quantity:
1 000
Part Number:
am79c961aKC
Manufacturer:
AMD
Quantity:
20 000
Company:
Part Number:
am79c961aKC/W
Quantity:
15
Part Number:
am79c961aKIW
Manufacturer:
AMD
Quantity:
20 000
Part Number:
am79c961aVC
Manufacturer:
AMD
Quantity:
1 831
Part Number:
am79c961aVC/W
Manufacturer:
RENES
Quantity:
2 147
SWITCHING CHARACTERISTICS: GPSI (Unless otherwise noted, parametric values are
the same between Commercial devices and Industrial devices)
Notes:
1. CLSN must be asserted for a continuous period of 110 ns or more. Assertion for less than 110 ns period may or may
2. RCLK should meet jitter requirements of IEEE 802.3 specification.
3. CLSN assertion before 51.2 s will be indicated as a normal collision. CLSN assertion after 51.2 s will be
146
Transmit Timing
Receive Timing
not result in CLSN recognition.
considered as a Late Receive Collision.
Parameter
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
GPR10
GPR11
GPR12
GPR1
GPR2
GPR3
GPR4
GPR5
GPR6
GPR7
GPR8
GPR9
GPT1
GPT2
GPT3
GPT4
GPT5
GPT6
GPT7
GPT8
GPT9
STDCLK Period (802.3 Compliant)
STDCLK HIGH Time
TXDAT and TXEN Delay from
RXCRS Setup to
RXCRS Hold from
CLSN Active Time to Trigger Collision
CLSN Active to
LCAR Assertion
CLSN Active to
Hearbeat Window
CLSN Active to
SRDCLK Period
SRDCLK High Time
SRDCLK Low Time
RXDAT and RXCRS Setup to
RXDAT Hold from
RXCRS Hold from
CLSN Active to First
(Collision Recognition)
CLSN Active to
Designation Bit
CLSN Setup to last
Collision Recognition
CLSN Active
CLSN Inactive Setup to First
CLSN Inactive Hold to Last
SRDCLK
Parameter Description
RXCRS for Normal Collision
RXCRS to Prevent
RXCRS for SQE
SRDCLK for Address Type
STDCLK (Last Bit)
RCLK
TENA
SRDCLK
SRDCLK for
SRDCLK
RCLK
RCLK
TCLK
Am79C961A
Test Conditions
(Note 1)
(Note 2)
(Note 2)
(Note 2)
(Note 3)
99.99
51.2
Min
210
110
210
110
300
300
40
80
30
30
15
15
0
0
0
0
0
0
0
100.01
Max
51.2
120
4.0
60
70
80
80
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s

Related parts for am79c961a