am79c961a Advanced Micro Devices, am79c961a Datasheet - Page 73

• Manufacturer Part Number: am79c961a
• Description: Pcnet?-isa Ii Jumperless, Full Duplex Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

below 4 s will rarely be encountered on a correctly
configured network, and since the fragment size will be
larger than the 4 s blinding window, then the IPG
counter will be reset by a worst case IPG shrinkage/
fragment scenario and the PCnet-ISA II controller will
defer its transmission. In addition, the PCnet-ISA II
controller will not restart the “blinding” period if carrier
is detected within the 4.0 s – 6.0 s IFS1 period, but
will commence timing of the entire IFS1 period.
Contention resolution (collision handling)
Collision detection is performed and reported to the
MAC engine by the integrated Manchester Encoder/
Decoder (MENDEC).
If a collision is detected before the complete preamble/
SFD sequence has been transmitted, the MAC Engine
will complete the preamble/SFD before appending the
jam sequence. If a collision is detected after the pream-
ble/SFD has been completed, but prior to 512 bits
being transmitted, the MAC Engine will abort the trans-
mission, and append the jam sequence immediately.
The jam sequence is a 32-bit all zeroes pattern.
The MAC Engine will attempt to transmit a frame a total
of 16 times (initial attempt plus 15 retries) due to normal
collisions (those within the slot time). Detection of colli-
sion will cause the transmission to be re-scheduled,
dependent on the backoff time that the MAC Engine
computes. If a single retry was required, the ONE bit
will be set in the Transmit Frame Status (TMD1 in the
Transmit Descriptor Ring). If more than one retry was
required, the MORE bit will be set. If all 16 attempts ex-
perienced collisions, the RTRY bit (in TMD3) will be set
(ONE and MORE will be clear), and the transmit mes-
sage will be flushed from the FIFO. If retries have been
disabled by setting the DRTY bit in the MODE register
(CSR15), the MAC Engine will abandon transmission
of the frame on detection of the first collision. In this
case, only the RTRY bit will be set and the transmit
message will be flushed from the FIFO.
If a collision is detected after 512 bit times have been
transmitted, the collision is termed a late collision. The
MAC Engine will abort the transmission, append the
jam sequence, and set the LCOL bit. No retry attempt
will be scheduled on detection of a late collision, and
the FIFO will be flushed.
s after a transmission. However, since IPG shrinkage
Am79C961A
The IEEE 802.3 Standard requires use of a “truncated
binary exponential backoff” algorithm which provides a
controlled pseudo-random mechanism to enforce the
collision backoff interval, before re-transmission is
attempted.
The PCnet-ISA II controller provides an alternative
algorithm, which suspends the counting of the slot
time/IPG during the time that receive carrier sense is
detected. This algorithm aids in networks where large
numbers of nodes are present, and numerous nodes
can be in collision. The algorithm effectively acceler-
ates the increase in the backoff time in busy networks,
and allows nodes not involved in the collision to access
the channel while the colliding nodes await a reduction
in channel activity. Once channel activity is reduced,
the nodes resolving the collision time out their slot time
counters as normal.
Manchester Encoder/Decoder (MENDEC)
The integrated Manchester Encoder/Decoder provides
the PLS (Physical Layer Signaling) functions required
for a fully compliant IEEE 802.3 station. The MENDEC
provides the encoding function for data to be transmit-
ted on the network using the high accuracy on-board
oscillator, driven by either the crystal oscillator or an ex-
ternal CMOS-level compatible clock. The MENDEC
also provides the decoding function from data received
from the network. The MENDEC contains a Power On
Reset (POR) circuit, which ensures that all analog por-
tions of the PCnet-ISA II controller are forced into their
correct state during power-up, and prevents erroneous
data transmission and/or reception during this time.
External Crystal Characteristics
When using a crystal to drive the oscillator, the crystal
specification shown in the specification table may be
used to ensure less than 0.5 ns jitter at DO .
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:
“At the end of enforcing a collision (jamming),
the CSMA/CD sublayer delays before attempt-
ing to re-transmit the frame. The delay is an in-
teger multiple of slot Time. The number of slot
times to delay before the nth re-transmission
attempt is chosen as a uniformly distributed
random integer r in the range:
0
r < 2 k , where k = min (n,10).”
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