am79c961a Advanced Micro Devices, am79c961a Datasheet - Page 91

• Manufacturer Part Number: am79c961a
• Description: Pcnet?-isa Ii Jumperless, Full Duplex Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

to be inserted. The PCnet-ISA II controller will append
pad bytes dependent on the actual number of bits
transmitted onto the network. Once the last data byte of
the frame has completed prior to appending the FCS,
the PCnet-ISA II controller will check to ensure that 544
bits have been transmitted. If not, pad bytes are added
to extend the frame size to this value, and the FCS is
then added.
The 544 bit count is derived from the following:
To be classed as a minimum-size frame at the receiver,
the transmitted frame must contain:
At the point that FCS is to be appended, the transmitted
frame should contain:
A minimum-length transmit frame from the PCnet-ISA
II controller will, therefore, be 576 bits after the FCS is
appended.
Transmit FCS Generation
Automatic generation and transmission of FCS for a
transmit frame depends on the value of DXMTFCS bit
in CSR15. When DXMTFCS = 0 the transmitter will
Minimum frame size (excluding preamble,
including FCS)
Preamble/SFD size
Preamble + (Min Frame Size + FCS) bits
Preamble + (Min Frame Size - FCS) bits
FCS size
64+
1010....1010
Preamble
Bits
56
(512- 32) bits
64 bytes
8 bytes
4 bytes
10101011
SYNC
Bits
8
512 bits
64 bits
32 bits
ISO 8802-3 (IEEE/ANSI 802.3) Data Frame
ADDR
Bytes
Dest.
6
ADDR.
SRCE.
Bytes
6
Am79C961A
Length
generate and append the FCS to the transmitted frame.
I f t h e a u t o m a t i c p a d d i n g fe a t u r e i s i n vo k e d
(APAD_XMT is SET in CSR4), the FCS will be
appended by the PCnet-ISA II controller regardless of
the state of DXMTFCS. Note that the calculated FCS is
transmitted most-significant bit first. The default value
of DXMTFCS is 0 after RESET.
Transmit Exception Conditions
Exception conditions for frame transmission fall into
two distinct categories; those which are the result of
normal network operation, and those which occur due
to abnormal network and/or host related events.
Normal events which may occur and which are handled
autonomously by the PCnet-ISA II controller are basi-
cally collisions within the slot time with automatic retry.
The PCnet-ISA II controller will ensure that collisions
which occur within 512 bit times from the start of trans-
mission (including preamble) will be automatically
retried with no host intervention. The transmit FIFO en-
sures this by guaranteeing that data contained within
the FIFO will not be overwritten until at least 64 bytes
(512 bits) of data have been successfully transmitted
onto the network.
If 16 total attempts (initial attempt plus 15 retries) fail,
the PCnet-ISA II controller sets the RTRY bit in the cur-
rent transmit TDTE in host memory (TMD2), gives up
ownership (sets the OWN bit to zero) for this packet,
and processes the next packet in the transmit ring for
transmission.
Bytes
2
Data
LLC
46-1500
Bytes
Pad
FCS
Bytes
4
19364B-20
91