am79c961a Advanced Micro Devices, am79c961a Datasheet - Page 87

• Manufacturer Part Number: am79c961a
• Description: Pcnet?-isa Ii Jumperless, Full Duplex Single-chip Ethernet Controller For Isa
• Manufacturer: Advanced Micro Devices

lower priority DRQ pin than the one currently being
used by the PCnet-ISA II is asserted, the PCnet-ISA II
will wait 2.6 s after the deassertion of DACK before
re-asserting its DRQ pin. If no lower priority DRQ pin is
asserted, the PCnet-ISA II may re-assert its DRQ pin
after as short as 1.1 s following DACK deassertion.
The priorities assumed by the PCnet-ISA II are ordered
DRQ3, DRQ5, DRQ6, DRQ7, with DRQ3 having high-
est priority and DRQ7 having the lowest priority. This
priority ordering matches that used by typical ISA bus
DMA controllers.
This adaptive delay scheme allows for fair bus band-
width sharing when two bus mastering devices, e.g.
two PCnet-ISA II devices, are on an ISA bus. The con-
troller using the higher priority DMA channel cannot
lock out the controller using the lower priority DMA
channel because of the 2.6 s delay that is inserted
before DRQ reassertion when a lower priority DRQ pin
is asserted. When there is no lower priority DMA
request asserted, the PCnet-ISA II re-requests the bus
immediately, providing optimal performance when
there is no competition for bus access.
Bus Slave Mode
The PCnet-ISA II can be configured to be a bus slave
for systems that do not support bus mastering or
require a local memory to tolerate high bus latencies.
In the Bus Slave mode, the I/O map of the PCnet-ISA
II is identical to the I/O map when in the Bus Master
mode (see I/O Resources section). Hence, the address
PROM, controller registers, and Reset por t are
accessed through I/O cycles on the ISA bus. However,
the initialization block, descriptor rings, and buffers,
which are located in system memory when in the Bus
Master mode, are located in a local SRAM when in the
Bus Slave mode. The local SRAM can be accessed by
memory cycles on the ISA bus (Shared Memory archi-
tecture) or by I/O cycles on the ISA bus (Programmed
I/O mode).
Address PROM Cycles External PROM
The Address PROM is a small (16 bytes) 8-bit PROM
connected to the PCnet-ISA II controller Private Data
Bus (PRDB). The PCnet-ISA II controller will support
only 8-bit ISA I/O bus cycles for the address PROM;
this limitation is transparent to software and does not
preclude 16-bit software I/O accesses. An access cycle
begins with the Permanent Master driving AEN LOW,
driving the addresses valid, and driving IOR active. The
PCnet-ISA II controller detects this combination of sig-
nals and arbitrates for the Private Data Bus if neces-
sary. IOCHRDY is always driven LOW during address
PROM accesses.
When the Private Data Bus becomes available, the
PCnet-ISA II controller drives APCS active, releases
IOCHRDY, turns on the data path from PRD0-7, and
enables the SD0-7 drivers (but not SD8-15). During
Am79C961A
this bus cycle, IOCS16 is not driven active. This condi-
tion is maintained until IOR goes inactive, at which time
the access cycle ends. Data is removed from SD0-7
within 30 ns.
The PCnet-ISA II controller will perform 8-bit ISA bus
cycle operation for all resources (registers, PROMs,
SRAM) if SBHE has been left unconnected, such as in
the case of an 8-bit system like the PC/XT.
Ethernet Controller Register Cycles
Ethernet controller registers (RAP, RDP, ISACSR) are
naturally 16-bit resources but can be configured to
operate with 8-bit bus cycles provided the proper pro-
tocol is followed. This is programmable by the
EEPROM. This means on a read, the PCnet-ISA II con-
troller will only drive the low byte of the system data
bus; if an odd byte is accessed, it will be swapped
down. The high byte of the system data bus is never
driven by the PCnet-ISA II controller under these con-
ditions. On a write, the even byte is placed in a holding
register. An odd-byte write is internally swapped up and
augmented with the even byte in the holding register to
provide an internal 16-bit write. This allows the use of
8-bit I/O bus cycles which are more likely to be compat-
ible with all clones, but requires that both bytes be writ-
ten in immediate succession. This is accomplished
simply by treating the PCnet-ISA II controller controller
registers as 16-bit software resources. The mother-
board will convert the 16-bit accesses done by soft-
ware into two sequential 8-bit accesses, an even-byte
access followed immediately by an odd-byte access.
An access cycle begins with the Permanent Master
driving AEN LOW, driving the address valid, and driv-
ing IOR or IOW active. The PCnet-ISA II controller de-
tects this combination of signals and drives IOCHRDY
LOW. IOCS16 will also be driven LOW if 16-bit I/O bus
cycles are enabled. When the register data is ready,
IOCHRDY will be released HIGH. This condition is
maintained until IOR or IOW goes inactive, at which
time the bus cycle ends.
The PCnet-ISA II controller will perform 8-bit ISA bus
cycle operation for all resources (registers, PROMs,
SRAM) if SBHE has been left unconnected, such as in
the case of an 8-bit system like the PC/XT.
RESET Cycles
A read to the reset address causes an PCnet-ISA II
controller reset. This has the same effect as asserting
the RESET pin on the PCnet-ISA
happens on system power up or on a hard boot) except
that the T-MAU is NOT reset. The T-MAU will retain its
link pass/fail state, disregarding the software RESET
command. The subsequent write cycle needed in the
NE2100 LANCE- based family of Ethernet cards is not
required but does not have any harmful effects.
IOCS16 is not asserted in this cycle.
+
controller (which
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