am79c850 Advanced Micro Devices, am79c850 Datasheet - Page 15

• Manufacturer Part Number: am79c850
• Description: Supernet-r 3
• Manufacturer: Advanced Micro Devices

word and the descriptor word at the end of the frame. In
transmit mode, when BDTAG = 0, it indicates that the
information on the BD bus is data, i.e., end-of-frame not
yet reached.
CSO
Chip-Select Output (TTL output, high impedance,
active low)
The chip-select output (active low) is a select signal for
buffer memory read and write operations. This line is in
the high-impedance state when buffer memory control
is released to the NP.
RD
Buffer Memory Read (TTL output, high
impedance, active low)
This output signal (active low) controls the buffer
memory during a buffer-memory read accesses. This
line is in the high-impedance state when buffer memory
control is released to the NP.
WR
Buffer Memory Write (TTL output, high
impedance, active low)
This (active low) output signal, in its active-low state,
allows write accesses to buffer memory. This line is in
the high-impedance state when buffer memory control
is released to the NP.
Host/Buffer Memory Interface (10 Pins)
All these signals are synchronous to BMCLK.
HSACK
Host Acknowledge (TTL output, high impedance)
This signal indicates that the current host read/write
request is being granted by SUPERNET 3 and allows
read/write accesses of buffer memory by the host.
HSREQ2–0
Host Request Bus (TTL input)
The host request bus specifies to SUPERNET 3 the type
of buffer memory access the host requires, as described
in the following table.
Special-frame write requests are used to set up claim,
beacon, and auto-void frames in the buffer memory (see
the discussion under Buffer Memory Operation in
SUPERNET 2 data book). These requests make use of
the WPXSF register to set up special frames in the
special-frame area.
Read request is used to retrieve received frames from
buffer memory and store them in the system memory.
Write requests are used to set up frames in buffer
memory for transmission.
P R E L I M I N A R Y
SUPERNET 3
Note: * Only if two receive queue operation is selected
through MDREG3.
QCTRL2–0
Buffer Queue Control (TTL output, high
impedance)
The QCTRL2–0 status output lines are encoded as de-
scribed in the following table.
HSREQ2
0
0
0
0
1
1
1
1
HSREQ1
0
0
1
1
0
0
1
1
HSREQ0
0
1
0
1
0
1
0
1
Type of Request
None.
Read Request:
Second Receive
Queue*
Special Frame
Write Request.
Read Request:
Receive Queue.
Write Request:
Synchronous Queue.
Write Request:
Asynchronous
Queue 0.
Write Request:
Asynchronous
Queue 1.
Write Request
Asynchronous
Queue 1.
AMD
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