am79c850 Advanced Micro Devices, am79c850 Datasheet - Page 23

• Manufacturer Part Number: am79c850
• Description: Supernet-r 3
• Manufacturer: Advanced Micro Devices

Transmit Queues
ASYNC2 Transmit Queue Not Supported
The SUPERNET 3 supports SYNCHRONOUS, and two
ASYNCHRONOUS priorities. The ASYNC2 queue is no
longer supported. This causes the following changes:
1. TPRI2 (16-bit priority register for asynchronous
2. EAA2, WPXA2, SWPXA2, RPXA2 registers are no
3. The ‘Clear Asynchronous Queue 2 Lock’ and
4. The STEFRMA2, STECFRMA2 and STXABRA2
5. The QCTRL[2:0] = 100 encoding is now invalid. This
6. The HSREQ[2:0] = 111 is now decoded as “Write
Note: If the encoding HSREQ[2:0] = 111 is used, the
SUPERNET 3 would not use the QCTRL[2:0] = 100
queue 2) is no longer implemented.
longer implemented.
‘Transmit Asynchronous Queue 2’ commands are
no longer available in the command registers 1 and
2, respectively. The value 0x18 in command register
1 and 0x08 in command register 2 shall not be
decoded to any other instruction. These values are
reserved.
bits in the upper 16 bits of the status register 1
(ST1U) are reserved and set to zero. Similarly
SQLCK2, STXINFLA2, SPCEPDA2, and STBURA2
are reserved and set to zero.
encoding
Asynchronous Queue 2’ which is no longer
available. The encoding is reserved and shall not be
used to indicate any other QCTRL condition. (See
NOTE)
Request: Asynchronous Queue 1”. In FORMAC+
this
asynchronous queue 2 which is no longer available.
(MDREG 2 bit 11)
(MDREG 2 bit 11)
Case 1: LSB = 0
Case 1: LSB = 1
request
indicated
indicated
Then FC starts at:
Then FC starts at:
‘Request
If MENFCLOC 13-12 =
a
write
transfer
request
P R E L I M I N A R Y
SUPERNET 3
(MSBYTE)
(MSBYTE)
into
to
Byte 1
Byte 4
00
encoding to indicate status of Asynchronous Queue, but
instead the QCTRL[2:0] = 011 (“Request transfer into
Asynchronous Queue 1”) encoding would be indicated
by SUPERNET 3 and external logic could be added to
invert this encoding to be compatible with FORMAC+.
AFULL Encoding of QCTRL Signals Modified
The QCTRL2–0 pins provide the encoded status of the
buffer memory transmit queues. The value QCTRL[2:0]
= 111, ‘Current queue almost full’, was asserted for one
host write cycle in SUPERNET 2. This signal shall now
be generated for every host write cycle until the queue
becomes full or the almost full threshold is no
longer exceeded.
This new signal assertion is implemented only if the bit
MENAFULL is set in mode register 3 (MDREG3)
Transmit Frame Format
In SUPERNET 2 transmit frames must consist of
aligned data, i.e. all words in the buffer memory must
contain four valid bytes, except that the last data word
may consist of less than four bytes. This required that
the Frame Control (FC) of the frame be written as the
most significant byte of the frame data long word.
SUPERNET 3 would support an enhanced feature,
where in the Frame Control (FC) could be any byte of the
frame data long word. The Destination Address (DA)
would follow the FC as the next byte in any mode of
operation. This feature is enabled only when the bits
MENFCLOC (bit 12 & 13) is set in mode register 3
(MDREG3). Upon reset these bits would be both zero
and the Frame Control (FC) has to be written as the
most significant byte of the frame data long word. The
following table describes the decoding of the
MENFCLOC bits in the mode register 3 (MDREG 3):
Byte 2
Byte 3
01
Byte 3
Byte 2
10
(LSBYTE)
(LSBYTE)
Byte 4
Byte 1
11
AMD
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