am79c850 Advanced Micro Devices, am79c850 Datasheet - Page 36

• Manufacturer Part Number: am79c850
• Description: Supernet-r 3
• Manufacturer: Advanced Micro Devices

Instructions Supported
This section describes the public and private instruc-
tions that are supported in this implementation. The
instruction register is a 4-bit register. The least
EXTEST Instruction
The EXTEST instruction is used to test board level
interconnect and for testing of circuitry external to
SUPERNET 3. This instruction selects the Boundary
Scan register (BSR) for scanning between TDI and TDO
when in the Shift-DR controller state. During execution:
1. SUPERNET 3 outputs are driven from the Parallel
2. SUPERNET 3 internal outputs are sampled into the
3. SUPERNET 3 inputs are sampled into the BSR.
4. SUPERNET 3 internal inputs are driven from the
IDCODE Instruction
The IDCODE instruction is provided for access to the
manufacturer’s identity, the part number, and the
version of the SUPERNET 3. This instruction selects the
32-bit identification register for scanning between TDI
and TDO in the Shift-DR controller state. The IDCODE
instruction is forced into the instruction registers parallel
output latches during the Test-Logic-Reset controller
state. The 32 bits of the identification register are broken
down as follows:
36
IDREG[31:0]
Data register (PDR).
BSR.
Parallel Data register (PDR).
IDREG[31:28]
IDREG[27:12]
IDREG[11:1]
IDREG[0]
AMD
Bits
Instruction
EXTEST
IDCODE
SAMPLE
TRI_ST
RUNBIST
SCANBIST
BYPASS
Version number (initially 0001)
Part number - 2870 (Hex)
Manufacturer’s ID. The 11-bit
manufacturer’s ID. for AMD is
00000000001 according to JEDEC
publication 106-A.
Always set to logic 1.
Value = 1287 0003 (Hex)
Description
Description
External test
Device identification
Sample/preload B.S.R.
Force outputs to Hi-Z
Self-test
Manufacturing Testing
Bypass register scan
P R E L I M I N A R Y
SUPERNET 3
significant bit of the instruction register is the bit nearest
the TDO output. The encoding of the instructions is
as follows:
SAMPLE Instruction
The SAMPLE/PRELOAD instruction is used to observe
the normal operation of the SUPERNET 3 without
affecting system operation. It is also used to load values
into the PDR prior to the selection of another instruction.
This instruction selects the BSR for scanning between
TDI and TDO during the Shift-DR controller state.
During execution:
1. SUPERNET
2. SUPERNET 3 internal outputs are sampled into the
3. SUPERNET 3 inputs are sampled into the BSR.
4. SUPERNET 3 internal inputs are driven from the
TRI_ST Instruction
The TRI_ST instruction is provided for easy tri-state of
all SUPERNET 3 outputs. This instruction selects the
bypass register for scanning between TDI and TDO
during the Shift-DR controller state.
RUNBIST Instruction
The RUNBIST instruction is provided for self-test of the
SUPERNET 3. This instruction must not be selected
during the normal operation of the part.
Once the RUNBIST instruction is selected, the BIST
operation is enabled by applying a minimum of 65000
TCK clock cycles while in the RUN-TEST/IDLE TAP
controller state. Once the minimum number of clock
cycles
SCANBIST instruction.
SCANBIST Instruction
The SCANBIST instruction selects the BIST result
register for scanning between TDI and TDO during the
Shift-DR controller state. The BIST results can be
SUPERNET 3.
BSR.
SUPERNET 3 inputs.
BIST Execution
Reg. Selected
Scan Results
have
Bypass
Bypass
IDREG
B.S.R.
B.S.R.
elapsed,
3
outputs
proceed
are
INST[3:0]
driven
0000
0001
0010
0011
0101
0110
1111
to
load
by
the
the